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hw/loongarch: virt: support up to 4 serial ports

Browse source 
In order to support additional channels of communication using
`-serial`, add several serial ports, up to the standard 4 generally
supported by the 8250 driver.

Fixed: https://lore.kernel.org/all/20240907143439.2792924-1-Jason@zx2c4.com/

Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
Tested-by: Bibo Mao <maobibo@loongson.cn>
[gaosong: ACPI uart need't reverse order]
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20240907143439.2792924-1-Jason@zx2c4.com>
This commit is contained in:
Jason A. Donenfeld 2024-09-07 16:34:39 +02:00 • committed by Song Gao
parent 32c22cc47c
commit b3d4ef8348
3 changed files with 36 additions and 21 deletions
Download patch file Download diff file Expand all files Collapse all files

21
hw/loongarch/acpi-build.c
View file

@ -31,6 +31,7 @@
#include "hw/acpi/generic_event_device.h" #include "hw/acpi/generic_event_device.h"
#include "hw/pci-host/gpex.h" #include "hw/pci-host/gpex.h"
#include "sysemu/sysemu.h"
#include "sysemu/tpm.h" #include "sysemu/tpm.h"
#include "hw/platform-bus.h" #include "hw/platform-bus.h"
#include "hw/acpi/aml-build.h" #include "hw/acpi/aml-build.h"
@ -252,23 +253,27 @@ struct AcpiBuildState {
MemoryRegion *linker_mr; MemoryRegion *linker_mr;
} AcpiBuildState; } AcpiBuildState;
static void build_uart_device_aml(Aml *table) static void build_uart_device_aml(Aml *table, int index)
{ {
Aml *dev; Aml *dev;
Aml *crs; Aml *crs;
Aml *pkg0, *pkg1, *pkg2; Aml *pkg0, *pkg1, *pkg2;
uint32_t uart_irq = VIRT_UART_IRQ; Aml *scope;
uint32_t uart_irq;
uint64_t base;
Aml *scope = aml_scope("_SB"); uart_irq = VIRT_UART_IRQ + index;
dev = aml_device("COMA"); base = VIRT_UART_BASE + index * VIRT_UART_SIZE;
scope = aml_scope("_SB");
dev = aml_device("COM%d", index);
aml_append(dev, aml_name_decl("_HID", aml_string("PNP0501"))); aml_append(dev, aml_name_decl("_HID", aml_string("PNP0501")));
aml_append(dev, aml_name_decl("_UID", aml_int(0))); aml_append(dev, aml_name_decl("_UID", aml_int(index)));
aml_append(dev, aml_name_decl("_CCA", aml_int(1))); aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
crs = aml_resource_template(); crs = aml_resource_template();
aml_append(crs, aml_append(crs,
aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
AML_NON_CACHEABLE, AML_READ_WRITE, AML_NON_CACHEABLE, AML_READ_WRITE,
0, VIRT_UART_BASE, VIRT_UART_BASE + VIRT_UART_SIZE - 1, 0, base, base + VIRT_UART_SIZE - 1,
0, VIRT_UART_SIZE)); 0, VIRT_UART_SIZE));
aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
AML_SHARED, &uart_irq, 1)); AML_SHARED, &uart_irq, 1));
@ -401,6 +406,7 @@ static void acpi_dsdt_add_tpm(Aml *scope, LoongArchVirtMachineState *vms)
static void static void
build_dsdt(GArray *table_data, BIOSLinker *linker, MachineState *machine) build_dsdt(GArray *table_data, BIOSLinker *linker, MachineState *machine)
{ {
int i;
Aml *dsdt, *scope, *pkg; Aml *dsdt, *scope, *pkg;
LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(machine); LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(machine);
AcpiTable table = { .sig = "DSDT", .rev = 1, .oem_id = lvms->oem_id, AcpiTable table = { .sig = "DSDT", .rev = 1, .oem_id = lvms->oem_id,
@ -408,7 +414,8 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, MachineState *machine)
acpi_table_begin(&table, table_data); acpi_table_begin(&table, table_data);
dsdt = init_aml_allocator(); dsdt = init_aml_allocator();
build_uart_device_aml(dsdt); for (i = 0; i < VIRT_UART_COUNT; i++)
build_uart_device_aml(dsdt, i);
build_pci_device_aml(dsdt, lvms); build_pci_device_aml(dsdt, lvms);
build_la_ged_aml(dsdt, machine); build_la_ged_aml(dsdt, machine);
build_flash_aml(dsdt, lvms); build_flash_aml(dsdt, lvms);

25
hw/loongarch/virt.c
View file

@ -280,10 +280,10 @@ static void fdt_add_rtc_node(LoongArchVirtMachineState *lvms,
} }
static void fdt_add_uart_node(LoongArchVirtMachineState *lvms, static void fdt_add_uart_node(LoongArchVirtMachineState *lvms,
uint32_t *pch_pic_phandle) uint32_t *pch_pic_phandle, hwaddr base,
int irq, bool chosen)
{ {
char *nodename; char *nodename;
hwaddr base = VIRT_UART_BASE;
hwaddr size = VIRT_UART_SIZE; hwaddr size = VIRT_UART_SIZE;
MachineState *ms = MACHINE(lvms); MachineState *ms = MACHINE(lvms);
@ -292,9 +292,9 @@ static void fdt_add_uart_node(LoongArchVirtMachineState *lvms,
qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "ns16550a"); qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "ns16550a");
qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0x0, base, 0x0, size); qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0x0, base, 0x0, size);
qemu_fdt_setprop_cell(ms->fdt, nodename, "clock-frequency", 100000000); qemu_fdt_setprop_cell(ms->fdt, nodename, "clock-frequency", 100000000);
if (chosen)
qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename); qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename);
qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", irq, 0x4);
VIRT_UART_IRQ - VIRT_GSI_BASE, 0x4);
qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent", qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent",
*pch_pic_phandle); *pch_pic_phandle);
g_free(nodename); g_free(nodename);
@ -706,11 +706,18 @@ static void virt_devices_init(DeviceState *pch_pic,
/* Add pcie node */ /* Add pcie node */
fdt_add_pcie_node(lvms, pch_pic_phandle, pch_msi_phandle); fdt_add_pcie_node(lvms, pch_pic_phandle, pch_msi_phandle);
serial_mm_init(get_system_memory(), VIRT_UART_BASE, 0, /*
qdev_get_gpio_in(pch_pic, * Create uart fdt node in reverse order so that they appear
VIRT_UART_IRQ - VIRT_GSI_BASE), * in the finished device tree lowest address first
115200, serial_hd(0), DEVICE_LITTLE_ENDIAN); */
fdt_add_uart_node(lvms, pch_pic_phandle); for (i = VIRT_UART_COUNT; i --> 0;) {
hwaddr base = VIRT_UART_BASE + i * VIRT_UART_SIZE;
int irq = VIRT_UART_IRQ + i - VIRT_GSI_BASE;
serial_mm_init(get_system_memory(), base, 0,
qdev_get_gpio_in(pch_pic, irq),
115200, serial_hd(i), DEVICE_LITTLE_ENDIAN);
fdt_add_uart_node(lvms, pch_pic_phandle, base, irq, i == 0);
}
/* Network init */ /* Network init */
pci_init_nic_devices(pci_bus, mc->default_nic); pci_init_nic_devices(pci_bus, mc->default_nic);

9
include/hw/pci-host/ls7a.h
View file

@ -36,17 +36,18 @@
#define VIRT_PCH_PIC_IRQ_NUM 32 #define VIRT_PCH_PIC_IRQ_NUM 32
#define VIRT_GSI_BASE 64 #define VIRT_GSI_BASE 64
#define VIRT_DEVICE_IRQS 16 #define VIRT_DEVICE_IRQS 16
#define VIRT_UART_COUNT 4
#define VIRT_UART_IRQ (VIRT_GSI_BASE + 2) #define VIRT_UART_IRQ (VIRT_GSI_BASE + 2)
#define VIRT_UART_BASE 0x1fe001e0 #define VIRT_UART_BASE 0x1fe001e0
#define VIRT_UART_SIZE 0X100 #define VIRT_UART_SIZE 0x100
#define VIRT_RTC_IRQ (VIRT_GSI_BASE + 3) #define VIRT_RTC_IRQ (VIRT_GSI_BASE + 6)
#define VIRT_MISC_REG_BASE (VIRT_PCH_REG_BASE + 0x00080000) #define VIRT_MISC_REG_BASE (VIRT_PCH_REG_BASE + 0x00080000)
#define VIRT_RTC_REG_BASE (VIRT_MISC_REG_BASE + 0x00050100) #define VIRT_RTC_REG_BASE (VIRT_MISC_REG_BASE + 0x00050100)
#define VIRT_RTC_LEN 0x100 #define VIRT_RTC_LEN 0x100
#define VIRT_SCI_IRQ (VIRT_GSI_BASE + 4) #define VIRT_SCI_IRQ (VIRT_GSI_BASE + 7)
#define VIRT_PLATFORM_BUS_BASEADDRESS 0x16000000 #define VIRT_PLATFORM_BUS_BASEADDRESS 0x16000000
#define VIRT_PLATFORM_BUS_SIZE 0x2000000 #define VIRT_PLATFORM_BUS_SIZE 0x2000000
#define VIRT_PLATFORM_BUS_NUM_IRQS 2 #define VIRT_PLATFORM_BUS_NUM_IRQS 2
#define VIRT_PLATFORM_BUS_IRQ (VIRT_GSI_BASE + 5) #define VIRT_PLATFORM_BUS_IRQ (VIRT_GSI_BASE + 8)
#endif #endif