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hw/sh4: Coding style: Remove tabs

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Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Message-Id: <2d9b2c470ec022cc85a25b3e5de337b5e794f7f6.1635541329.git.balaton@eik.bme.hu>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
This commit is contained in:
BALATON Zoltan 2021-10-29 23:02:09 +02:00 • committed by Philippe Mathieu-Daudé
parent dd61b91c08
commit b3793b8a91
6 changed files with 1224 additions and 1225 deletions
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220
hw/intc/sh_intc.c
View file

@ -20,7 +20,7 @@
#define INTC_A7(x) ((x) & 0x1fffffff) #define INTC_A7(x) ((x) & 0x1fffffff)
void sh_intc_toggle_source(struct intc_source *source, void sh_intc_toggle_source(struct intc_source *source,
int enable_adj, int assert_adj) int enable_adj, int assert_adj)
{ {
int enable_changed = 0; int enable_changed = 0;
int pending_changed = 0; int pending_changed = 0;
@ -54,22 +54,22 @@ void sh_intc_toggle_source(struct intc_source *source,
if (source->parent->pending == 0) { if (source->parent->pending == 0) {
cpu_reset_interrupt(first_cpu, CPU_INTERRUPT_HARD); cpu_reset_interrupt(first_cpu, CPU_INTERRUPT_HARD);
} }
} }
} }
if (enable_changed || assert_adj || pending_changed) { if (enable_changed || assert_adj || pending_changed) {
#ifdef DEBUG_INTC_SOURCES #ifdef DEBUG_INTC_SOURCES
printf("sh_intc: (%d/%d/%d/%d) interrupt source 0x%x %s%s%s\n", printf("sh_intc: (%d/%d/%d/%d) interrupt source 0x%x %s%s%s\n",
source->parent->pending, source->parent->pending,
source->asserted, source->asserted,
source->enable_count, source->enable_count,
source->enable_max, source->enable_max,
source->vect, source->vect,
source->asserted ? "asserted " : source->asserted ? "asserted " :
assert_adj ? "deasserted" : "", assert_adj ? "deasserted" : "",
enable_changed == 1 ? "enabled " : enable_changed == 1 ? "enabled " :
enable_changed == -1 ? "disabled " : "", enable_changed == -1 ? "disabled " : "",
source->pending ? "pending" : ""); source->pending ? "pending" : "");
#endif #endif
} }
} }
@ -99,13 +99,13 @@ int sh_intc_get_pending_vector(struct intc_desc *desc, int imask)
for (i = 0; i < desc->nr_sources; i++) { for (i = 0; i < desc->nr_sources; i++) {
struct intc_source *source = desc->sources + i; struct intc_source *source = desc->sources + i;
if (source->pending) { if (source->pending) {
#ifdef DEBUG_INTC_SOURCES #ifdef DEBUG_INTC_SOURCES
printf("sh_intc: (%d) returning interrupt source 0x%x\n", printf("sh_intc: (%d) returning interrupt source 0x%x\n",
desc->pending, source->vect); desc->pending, source->vect);
#endif #endif
return source->vect; return source->vect;
} }
} }
abort(); abort();
@ -119,16 +119,16 @@ int sh_intc_get_pending_vector(struct intc_desc *desc, int imask)
#define INTC_MODE_IS_PRIO 8 #define INTC_MODE_IS_PRIO 8
static unsigned int sh_intc_mode(unsigned long address, static unsigned int sh_intc_mode(unsigned long address,
unsigned long set_reg, unsigned long clr_reg) unsigned long set_reg, unsigned long clr_reg)
{ {
if ((address != INTC_A7(set_reg)) && if ((address != INTC_A7(set_reg)) &&
(address != INTC_A7(clr_reg))) (address != INTC_A7(clr_reg)))
return INTC_MODE_NONE; return INTC_MODE_NONE;
if (set_reg && clr_reg) { if (set_reg && clr_reg) {
if (address == INTC_A7(set_reg)) if (address == INTC_A7(set_reg))
return INTC_MODE_DUAL_SET; return INTC_MODE_DUAL_SET;
else else
return INTC_MODE_DUAL_CLR; return INTC_MODE_DUAL_CLR;
} }
@ -139,12 +139,12 @@ static unsigned int sh_intc_mode(unsigned long address,
} }
static void sh_intc_locate(struct intc_desc *desc, static void sh_intc_locate(struct intc_desc *desc,
unsigned long address, unsigned long address,
unsigned long **datap, unsigned long **datap,
intc_enum **enums, intc_enum **enums,
unsigned int *first, unsigned int *first,
unsigned int *width, unsigned int *width,
unsigned int *modep) unsigned int *modep)
{ {
unsigned int i, mode; unsigned int i, mode;
@ -152,54 +152,54 @@ static void sh_intc_locate(struct intc_desc *desc,
if (desc->mask_regs) { if (desc->mask_regs) {
for (i = 0; i < desc->nr_mask_regs; i++) { for (i = 0; i < desc->nr_mask_regs; i++) {
struct intc_mask_reg *mr = desc->mask_regs + i; struct intc_mask_reg *mr = desc->mask_regs + i;
mode = sh_intc_mode(address, mr->set_reg, mr->clr_reg); mode = sh_intc_mode(address, mr->set_reg, mr->clr_reg);
if (mode == INTC_MODE_NONE) if (mode == INTC_MODE_NONE)
continue; continue;
*modep = mode; *modep = mode;
*datap = &mr->value; *datap = &mr->value;
*enums = mr->enum_ids; *enums = mr->enum_ids;
*first = mr->reg_width - 1; *first = mr->reg_width - 1;
*width = 1; *width = 1;
return; return;
} }
} }
if (desc->prio_regs) { if (desc->prio_regs) {
for (i = 0; i < desc->nr_prio_regs; i++) { for (i = 0; i < desc->nr_prio_regs; i++) {
struct intc_prio_reg *pr = desc->prio_regs + i; struct intc_prio_reg *pr = desc->prio_regs + i;
mode = sh_intc_mode(address, pr->set_reg, pr->clr_reg); mode = sh_intc_mode(address, pr->set_reg, pr->clr_reg);
if (mode == INTC_MODE_NONE) if (mode == INTC_MODE_NONE)
continue; continue;
*modep = mode | INTC_MODE_IS_PRIO; *modep = mode | INTC_MODE_IS_PRIO;
*datap = &pr->value; *datap = &pr->value;
*enums = pr->enum_ids; *enums = pr->enum_ids;
*first = (pr->reg_width / pr->field_width) - 1; *first = (pr->reg_width / pr->field_width) - 1;
*width = pr->field_width; *width = pr->field_width;
return; return;
} }
} }
abort(); abort();
} }
static void sh_intc_toggle_mask(struct intc_desc *desc, intc_enum id, static void sh_intc_toggle_mask(struct intc_desc *desc, intc_enum id,
int enable, int is_group) int enable, int is_group)
{ {
struct intc_source *source = desc->sources + id; struct intc_source *source = desc->sources + id;
if (!id) if (!id)
return; return;
if (!source->next_enum_id && (!source->enable_max || !source->vect)) { if (!source->next_enum_id && (!source->enable_max || !source->vect)) {
#ifdef DEBUG_INTC_SOURCES #ifdef DEBUG_INTC_SOURCES
printf("sh_intc: reserved interrupt source %d modified\n", id); printf("sh_intc: reserved interrupt source %d modified\n", id);
#endif #endif
return; return;
} }
if (source->vect) if (source->vect)
@ -237,7 +237,7 @@ static uint64_t sh_intc_read(void *opaque, hwaddr offset,
#endif #endif
sh_intc_locate(desc, (unsigned long)offset, &valuep, sh_intc_locate(desc, (unsigned long)offset, &valuep,
&enum_ids, &first, &width, &mode); &enum_ids, &first, &width, &mode);
return *valuep; return *valuep;
} }
@ -258,7 +258,7 @@ static void sh_intc_write(void *opaque, hwaddr offset,
#endif #endif
sh_intc_locate(desc, (unsigned long)offset, &valuep, sh_intc_locate(desc, (unsigned long)offset, &valuep,
&enum_ids, &first, &width, &mode); &enum_ids, &first, &width, &mode);
switch (mode) { switch (mode) {
case INTC_MODE_ENABLE_REG | INTC_MODE_IS_PRIO: break; case INTC_MODE_ENABLE_REG | INTC_MODE_IS_PRIO: break;
@ -270,11 +270,11 @@ static void sh_intc_write(void *opaque, hwaddr offset,
for (k = 0; k <= first; k++) { for (k = 0; k <= first; k++) {
mask = ((1 << width) - 1) << ((first - k) * width); mask = ((1 << width) - 1) << ((first - k) * width);
if ((*valuep & mask) == (value & mask)) if ((*valuep & mask) == (value & mask))
continue; continue;
#if 0 #if 0
printf("k = %d, first = %d, enum = %d, mask = 0x%08x\n", printf("k = %d, first = %d, enum = %d, mask = 0x%08x\n",
k, first, enum_ids[k], (unsigned int)mask); k, first, enum_ids[k], (unsigned int)mask);
#endif #endif
sh_intc_toggle_mask(desc, enum_ids[k], value & mask, 0); sh_intc_toggle_mask(desc, enum_ids[k], value & mask, 0);
} }
@ -301,11 +301,11 @@ struct intc_source *sh_intc_source(struct intc_desc *desc, intc_enum id)
} }
static unsigned int sh_intc_register(MemoryRegion *sysmem, static unsigned int sh_intc_register(MemoryRegion *sysmem,
struct intc_desc *desc, struct intc_desc *desc,
const unsigned long address, const unsigned long address,
const char *type, const char *type,
const char *action, const char *action,
const unsigned int index) const unsigned int index)
{ {
char name[60]; char name[60];
MemoryRegion *iomem, *iomem_p4, *iomem_a7; MemoryRegion *iomem, *iomem_p4, *iomem_a7;
@ -333,74 +333,74 @@ static unsigned int sh_intc_register(MemoryRegion *sysmem,
} }
static void sh_intc_register_source(struct intc_desc *desc, static void sh_intc_register_source(struct intc_desc *desc,
intc_enum source, intc_enum source,
struct intc_group *groups, struct intc_group *groups,
int nr_groups) int nr_groups)
{ {
unsigned int i, k; unsigned int i, k;
struct intc_source *s; struct intc_source *s;
if (desc->mask_regs) { if (desc->mask_regs) {
for (i = 0; i < desc->nr_mask_regs; i++) { for (i = 0; i < desc->nr_mask_regs; i++) {
struct intc_mask_reg *mr = desc->mask_regs + i; struct intc_mask_reg *mr = desc->mask_regs + i;
for (k = 0; k < ARRAY_SIZE(mr->enum_ids); k++) { for (k = 0; k < ARRAY_SIZE(mr->enum_ids); k++) {
if (mr->enum_ids[k] != source) if (mr->enum_ids[k] != source)
continue; continue;
s = sh_intc_source(desc, mr->enum_ids[k]); s = sh_intc_source(desc, mr->enum_ids[k]);
if (s) if (s)
s->enable_max++; s->enable_max++;
} }
} }
} }
if (desc->prio_regs) { if (desc->prio_regs) {
for (i = 0; i < desc->nr_prio_regs; i++) { for (i = 0; i < desc->nr_prio_regs; i++) {
struct intc_prio_reg *pr = desc->prio_regs + i; struct intc_prio_reg *pr = desc->prio_regs + i;
for (k = 0; k < ARRAY_SIZE(pr->enum_ids); k++) { for (k = 0; k < ARRAY_SIZE(pr->enum_ids); k++) {
if (pr->enum_ids[k] != source) if (pr->enum_ids[k] != source)
continue; continue;
s = sh_intc_source(desc, pr->enum_ids[k]); s = sh_intc_source(desc, pr->enum_ids[k]);
if (s) if (s)
s->enable_max++; s->enable_max++;
} }
} }
} }
if (groups) { if (groups) {
for (i = 0; i < nr_groups; i++) { for (i = 0; i < nr_groups; i++) {
struct intc_group *gr = groups + i; struct intc_group *gr = groups + i;
for (k = 0; k < ARRAY_SIZE(gr->enum_ids); k++) { for (k = 0; k < ARRAY_SIZE(gr->enum_ids); k++) {
if (gr->enum_ids[k] != source) if (gr->enum_ids[k] != source)
continue; continue;
s = sh_intc_source(desc, gr->enum_ids[k]); s = sh_intc_source(desc, gr->enum_ids[k]);
if (s) if (s)
s->enable_max++; s->enable_max++;
} }
} }
} }
} }
void sh_intc_register_sources(struct intc_desc *desc, void sh_intc_register_sources(struct intc_desc *desc,
struct intc_vect *vectors, struct intc_vect *vectors,
int nr_vectors, int nr_vectors,
struct intc_group *groups, struct intc_group *groups,
int nr_groups) int nr_groups)
{ {
unsigned int i, k; unsigned int i, k;
struct intc_source *s; struct intc_source *s;
for (i = 0; i < nr_vectors; i++) { for (i = 0; i < nr_vectors; i++) {
struct intc_vect *vect = vectors + i; struct intc_vect *vect = vectors + i;
sh_intc_register_source(desc, vect->enum_id, groups, nr_groups); sh_intc_register_source(desc, vect->enum_id, groups, nr_groups);
s = sh_intc_source(desc, vect->enum_id); s = sh_intc_source(desc, vect->enum_id);
if (s) { if (s) {
s->vect = vect->vect; s->vect = vect->vect;
@ -413,34 +413,34 @@ void sh_intc_register_sources(struct intc_desc *desc,
if (groups) { if (groups) {
for (i = 0; i < nr_groups; i++) { for (i = 0; i < nr_groups; i++) {
struct intc_group *gr = groups + i; struct intc_group *gr = groups + i;
s = sh_intc_source(desc, gr->enum_id); s = sh_intc_source(desc, gr->enum_id);
s->next_enum_id = gr->enum_ids[0]; s->next_enum_id = gr->enum_ids[0];
for (k = 1; k < ARRAY_SIZE(gr->enum_ids); k++) { for (k = 1; k < ARRAY_SIZE(gr->enum_ids); k++) {
if (!gr->enum_ids[k]) if (!gr->enum_ids[k])
continue; continue;
s = sh_intc_source(desc, gr->enum_ids[k - 1]); s = sh_intc_source(desc, gr->enum_ids[k - 1]);
s->next_enum_id = gr->enum_ids[k]; s->next_enum_id = gr->enum_ids[k];
} }
#ifdef DEBUG_INTC_SOURCES #ifdef DEBUG_INTC_SOURCES
printf("sh_intc: registered group %d (%d/%d)\n", printf("sh_intc: registered group %d (%d/%d)\n",
gr->enum_id, s->enable_count, s->enable_max); gr->enum_id, s->enable_count, s->enable_max);
#endif #endif
} }
} }
} }
int sh_intc_init(MemoryRegion *sysmem, int sh_intc_init(MemoryRegion *sysmem,
struct intc_desc *desc, struct intc_desc *desc,
int nr_sources, int nr_sources,
struct intc_mask_reg *mask_regs, struct intc_mask_reg *mask_regs,
int nr_mask_regs, int nr_mask_regs,
struct intc_prio_reg *prio_regs, struct intc_prio_reg *prio_regs,
int nr_prio_regs) int nr_prio_regs)
{ {
unsigned int i, j; unsigned int i, j;
@ -474,24 +474,24 @@ int sh_intc_init(MemoryRegion *sysmem,
reg_struct->action##_reg, #type, #action, j reg_struct->action##_reg, #type, #action, j
if (desc->mask_regs) { if (desc->mask_regs) {
for (i = 0; i < desc->nr_mask_regs; i++) { for (i = 0; i < desc->nr_mask_regs; i++) {
struct intc_mask_reg *mr = desc->mask_regs + i; struct intc_mask_reg *mr = desc->mask_regs + i;
j += sh_intc_register(sysmem, desc, j += sh_intc_register(sysmem, desc,
INT_REG_PARAMS(mr, mask, set, j)); INT_REG_PARAMS(mr, mask, set, j));
j += sh_intc_register(sysmem, desc, j += sh_intc_register(sysmem, desc,
INT_REG_PARAMS(mr, mask, clr, j)); INT_REG_PARAMS(mr, mask, clr, j));
} }
} }
if (desc->prio_regs) { if (desc->prio_regs) {
for (i = 0; i < desc->nr_prio_regs; i++) { for (i = 0; i < desc->nr_prio_regs; i++) {
struct intc_prio_reg *pr = desc->prio_regs + i; struct intc_prio_reg *pr = desc->prio_regs + i;
j += sh_intc_register(sysmem, desc, j += sh_intc_register(sysmem, desc,
INT_REG_PARAMS(pr, prio, set, j)); INT_REG_PARAMS(pr, prio, set, j));
j += sh_intc_register(sysmem, desc, j += sh_intc_register(sysmem, desc,
INT_REG_PARAMS(pr, prio, clr, j)); INT_REG_PARAMS(pr, prio, clr, j));
} }
} }
#undef INT_REG_PARAMS #undef INT_REG_PARAMS
@ -505,10 +505,10 @@ void sh_intc_set_irl(void *opaque, int n, int level)
struct intc_source *s = opaque; struct intc_source *s = opaque;
int i, irl = level ^ 15; int i, irl = level ^ 15;
for (i = 0; (s = sh_intc_source(s->parent, s->next_enum_id)); i++) { for (i = 0; (s = sh_intc_source(s->parent, s->next_enum_id)); i++) {
if (i == irl) if (i == irl)
sh_intc_toggle_source(s, s->enable_count?0:1, s->asserted?0:1); sh_intc_toggle_source(s, s->enable_count?0:1, s->asserted?0:1);
else else
if (s->asserted) if (s->asserted)
sh_intc_toggle_source(s, 0, -1); sh_intc_toggle_source(s, 0, -1);
} }
} }

34
hw/sh4/r2d.c
View file

@ -56,10 +56,10 @@
#define LINUX_LOAD_OFFSET 0x0800000 #define LINUX_LOAD_OFFSET 0x0800000
#define INITRD_LOAD_OFFSET 0x1800000 #define INITRD_LOAD_OFFSET 0x1800000
#define PA_IRLMSK 0x00 #define PA_IRLMSK 0x00
#define PA_POWOFF 0x30 #define PA_POWOFF 0x30
#define PA_VERREG 0x32 #define PA_VERREG 0x32
#define PA_OUTPORT 0x36 #define PA_OUTPORT 0x36
typedef struct { typedef struct {
uint16_t bcr; uint16_t bcr;
@ -96,19 +96,19 @@ enum r2d_fpga_irq {
}; };
static const struct { short irl; uint16_t msk; } irqtab[NR_IRQS] = { static const struct { short irl; uint16_t msk; } irqtab[NR_IRQS] = {
[CF_IDE] = { 1, 1<<9 }, [CF_IDE] = { 1, 1<<9 },
[CF_CD] = { 2, 1<<8 }, [CF_CD] = { 2, 1<<8 },
[PCI_INTA] = { 9, 1<<14 }, [PCI_INTA] = { 9, 1<<14 },
[PCI_INTB] = { 10, 1<<13 }, [PCI_INTB] = { 10, 1<<13 },
[PCI_INTC] = { 3, 1<<12 }, [PCI_INTC] = { 3, 1<<12 },
[PCI_INTD] = { 0, 1<<11 }, [PCI_INTD] = { 0, 1<<11 },
[SM501] = { 4, 1<<10 }, [SM501] = { 4, 1<<10 },
[KEY] = { 5, 1<<6 }, [KEY] = { 5, 1<<6 },
[RTC_A] = { 6, 1<<5 }, [RTC_A] = { 6, 1<<5 },
[RTC_T] = { 7, 1<<4 }, [RTC_T] = { 7, 1<<4 },
[SDCARD] = { 8, 1<<7 }, [SDCARD] = { 8, 1<<7 },
[EXT] = { 11, 1<<0 }, [EXT] = { 11, 1<<0 },
[TP] = { 12, 1<<15 }, [TP] = { 12, 1<<15 },
}; };
static void update_irl(r2d_fpga_t *fpga) static void update_irl(r2d_fpga_t *fpga)

509
hw/sh4/sh7750.c
View file

@ -60,17 +60,17 @@ typedef struct SH7750State {
uint16_t gpioic; uint16_t gpioic;
uint32_t pctra; uint32_t pctra;
uint32_t pctrb; uint32_t pctrb;
uint16_t portdira; /* Cached */ uint16_t portdira; /* Cached */
uint16_t portpullupa; /* Cached */ uint16_t portpullupa; /* Cached */
uint16_t portdirb; /* Cached */ uint16_t portdirb; /* Cached */
uint16_t portpullupb; /* Cached */ uint16_t portpullupb; /* Cached */
uint16_t pdtra; uint16_t pdtra;
uint16_t pdtrb; uint16_t pdtrb;
uint16_t periph_pdtra; /* Imposed by the peripherals */ uint16_t periph_pdtra; /* Imposed by the peripherals */
uint16_t periph_portdira; /* Direction seen from the peripherals */ uint16_t periph_portdira; /* Direction seen from the peripherals */
uint16_t periph_pdtrb; /* Imposed by the peripherals */ uint16_t periph_pdtrb; /* Imposed by the peripherals */
uint16_t periph_portdirb; /* Direction seen from the peripherals */ uint16_t periph_portdirb; /* Direction seen from the peripherals */
sh7750_io_device *devices[NB_DEVICES]; /* External peripherals */ sh7750_io_device *devices[NB_DEVICES]; /* External peripherals */
/* Cache */ /* Cache */
uint32_t ccr; uint32_t ccr;
@ -91,10 +91,10 @@ int sh7750_register_io_device(SH7750State * s, sh7750_io_device * device)
int i; int i;
for (i = 0; i < NB_DEVICES; i++) { for (i = 0; i < NB_DEVICES; i++) {
if (s->devices[i] == NULL) { if (s->devices[i] == NULL) {
s->devices[i] = device; s->devices[i] = device;
return 0; return 0;
} }
} }
return -1; return -1;
} }
@ -103,37 +103,37 @@ static uint16_t portdir(uint32_t v)
{ {
#define EVENPORTMASK(n) ((v & (1<<((n)<<1))) >> (n)) #define EVENPORTMASK(n) ((v & (1<<((n)<<1))) >> (n))
return return
EVENPORTMASK(15) | EVENPORTMASK(14) | EVENPORTMASK(13) | EVENPORTMASK(15) | EVENPORTMASK(14) | EVENPORTMASK(13) |
EVENPORTMASK(12) | EVENPORTMASK(11) | EVENPORTMASK(10) | EVENPORTMASK(12) | EVENPORTMASK(11) | EVENPORTMASK(10) |
EVENPORTMASK(9) | EVENPORTMASK(8) | EVENPORTMASK(7) | EVENPORTMASK(9) | EVENPORTMASK(8) | EVENPORTMASK(7) |
EVENPORTMASK(6) | EVENPORTMASK(5) | EVENPORTMASK(4) | EVENPORTMASK(6) | EVENPORTMASK(5) | EVENPORTMASK(4) |
EVENPORTMASK(3) | EVENPORTMASK(2) | EVENPORTMASK(1) | EVENPORTMASK(3) | EVENPORTMASK(2) | EVENPORTMASK(1) |
EVENPORTMASK(0); EVENPORTMASK(0);
} }
static uint16_t portpullup(uint32_t v) static uint16_t portpullup(uint32_t v)
{ {
#define ODDPORTMASK(n) ((v & (1<<(((n)<<1)+1))) >> (n)) #define ODDPORTMASK(n) ((v & (1<<(((n)<<1)+1))) >> (n))
return return
ODDPORTMASK(15) | ODDPORTMASK(14) | ODDPORTMASK(13) | ODDPORTMASK(15) | ODDPORTMASK(14) | ODDPORTMASK(13) |
ODDPORTMASK(12) | ODDPORTMASK(11) | ODDPORTMASK(10) | ODDPORTMASK(12) | ODDPORTMASK(11) | ODDPORTMASK(10) |
ODDPORTMASK(9) | ODDPORTMASK(8) | ODDPORTMASK(7) | ODDPORTMASK(6) | ODDPORTMASK(9) | ODDPORTMASK(8) | ODDPORTMASK(7) | ODDPORTMASK(6) |
ODDPORTMASK(5) | ODDPORTMASK(4) | ODDPORTMASK(3) | ODDPORTMASK(2) | ODDPORTMASK(5) | ODDPORTMASK(4) | ODDPORTMASK(3) | ODDPORTMASK(2) |
ODDPORTMASK(1) | ODDPORTMASK(0); ODDPORTMASK(1) | ODDPORTMASK(0);
} }
static uint16_t porta_lines(SH7750State * s) static uint16_t porta_lines(SH7750State * s)
{ {
return (s->portdira & s->pdtra) | /* CPU */ return (s->portdira & s->pdtra) | /* CPU */
(s->periph_portdira & s->periph_pdtra) | /* Peripherals */ (s->periph_portdira & s->periph_pdtra) | /* Peripherals */
(~(s->portdira | s->periph_portdira) & s->portpullupa); /* Pullups */ (~(s->portdira | s->periph_portdira) & s->portpullupa); /* Pullups */
} }
static uint16_t portb_lines(SH7750State * s) static uint16_t portb_lines(SH7750State * s)
{ {
return (s->portdirb & s->pdtrb) | /* CPU */ return (s->portdirb & s->pdtrb) | /* CPU */
(s->periph_portdirb & s->periph_pdtrb) | /* Peripherals */ (s->periph_portdirb & s->periph_pdtrb) | /* Peripherals */
(~(s->portdirb | s->periph_portdirb) & s->portpullupb); /* Pullups */ (~(s->portdirb | s->periph_portdirb) & s->portpullupb); /* Pullups */
} }
static void gen_port_interrupts(SH7750State * s) static void gen_port_interrupts(SH7750State * s)
@ -148,26 +148,26 @@ static void porta_changed(SH7750State * s, uint16_t prev)
#if 0 #if 0
fprintf(stderr, "porta changed from 0x%04x to 0x%04x\n", fprintf(stderr, "porta changed from 0x%04x to 0x%04x\n",
prev, porta_lines(s)); prev, porta_lines(s));
fprintf(stderr, "pdtra=0x%04x, pctra=0x%08x\n", s->pdtra, s->pctra); fprintf(stderr, "pdtra=0x%04x, pctra=0x%08x\n", s->pdtra, s->pctra);
#endif #endif
currenta = porta_lines(s); currenta = porta_lines(s);
if (currenta == prev) if (currenta == prev)
return; return;
changes = currenta ^ prev; changes = currenta ^ prev;
for (i = 0; i < NB_DEVICES; i++) { for (i = 0; i < NB_DEVICES; i++) {
if (s->devices[i] && (s->devices[i]->portamask_trigger & changes)) { if (s->devices[i] && (s->devices[i]->portamask_trigger & changes)) {
r |= s->devices[i]->port_change_cb(currenta, portb_lines(s), r |= s->devices[i]->port_change_cb(currenta, portb_lines(s),
&s->periph_pdtra, &s->periph_pdtra,
&s->periph_portdira, &s->periph_portdira,
&s->periph_pdtrb, &s->periph_pdtrb,
&s->periph_portdirb); &s->periph_portdirb);
} }
} }
if (r) if (r)
gen_port_interrupts(s); gen_port_interrupts(s);
} }
static void portb_changed(SH7750State * s, uint16_t prev) static void portb_changed(SH7750State * s, uint16_t prev)
@ -177,21 +177,21 @@ static void portb_changed(SH7750State * s, uint16_t prev)
currentb = portb_lines(s); currentb = portb_lines(s);
if (currentb == prev) if (currentb == prev)
return; return;
changes = currentb ^ prev; changes = currentb ^ prev;
for (i = 0; i < NB_DEVICES; i++) { for (i = 0; i < NB_DEVICES; i++) {
if (s->devices[i] && (s->devices[i]->portbmask_trigger & changes)) { if (s->devices[i] && (s->devices[i]->portbmask_trigger & changes)) {
r |= s->devices[i]->port_change_cb(portb_lines(s), currentb, r |= s->devices[i]->port_change_cb(portb_lines(s), currentb,
&s->periph_pdtra, &s->periph_pdtra,
&s->periph_portdira, &s->periph_portdira,
&s->periph_pdtrb, &s->periph_pdtrb,
&s->periph_portdirb); &s->periph_portdirb);
} }
} }
if (r) if (r)
gen_port_interrupts(s); gen_port_interrupts(s);
} }
/********************************************************************** /**********************************************************************
@ -201,20 +201,20 @@ static void portb_changed(SH7750State * s, uint16_t prev)
static void error_access(const char *kind, hwaddr addr) static void error_access(const char *kind, hwaddr addr)
{ {
fprintf(stderr, "%s to %s (0x" TARGET_FMT_plx ") not supported\n", fprintf(stderr, "%s to %s (0x" TARGET_FMT_plx ") not supported\n",
kind, regname(addr), addr); kind, regname(addr), addr);
} }
static void ignore_access(const char *kind, hwaddr addr) static void ignore_access(const char *kind, hwaddr addr)
{ {
fprintf(stderr, "%s to %s (0x" TARGET_FMT_plx ") ignored\n", fprintf(stderr, "%s to %s (0x" TARGET_FMT_plx ") ignored\n",
kind, regname(addr), addr); kind, regname(addr), addr);
} }
static uint32_t sh7750_mem_readb(void *opaque, hwaddr addr) static uint32_t sh7750_mem_readb(void *opaque, hwaddr addr)
{ {
switch (addr) { switch (addr) {
default: default:
error_access("byte read", addr); error_access("byte read", addr);
abort(); abort();
} }
} }
@ -225,30 +225,30 @@ static uint32_t sh7750_mem_readw(void *opaque, hwaddr addr)
switch (addr) { switch (addr) {
case SH7750_BCR2_A7: case SH7750_BCR2_A7:
return s->bcr2; return s->bcr2;
case SH7750_BCR3_A7: case SH7750_BCR3_A7:
if(!has_bcr3_and_bcr4(s)) if(!has_bcr3_and_bcr4(s))
error_access("word read", addr); error_access("word read", addr);
return s->bcr3; return s->bcr3;
case SH7750_FRQCR_A7: case SH7750_FRQCR_A7:
return 0; return 0;
case SH7750_PCR_A7: case SH7750_PCR_A7:
return s->pcr; return s->pcr;
case SH7750_RFCR_A7: case SH7750_RFCR_A7:
fprintf(stderr, fprintf(stderr,
"Read access to refresh count register, incrementing\n"); "Read access to refresh count register, incrementing\n");
return s->rfcr++; return s->rfcr++;
case SH7750_PDTRA_A7: case SH7750_PDTRA_A7:
return porta_lines(s); return porta_lines(s);
case SH7750_PDTRB_A7: case SH7750_PDTRB_A7:
return portb_lines(s); return portb_lines(s);
case SH7750_RTCOR_A7: case SH7750_RTCOR_A7:
case SH7750_RTCNT_A7: case SH7750_RTCNT_A7:
case SH7750_RTCSR_A7: case SH7750_RTCSR_A7:
ignore_access("word read", addr); ignore_access("word read", addr);
return 0; return 0;
default: default:
error_access("word read", addr); error_access("word read", addr);
abort(); abort();
} }
} }
@ -260,11 +260,11 @@ static uint32_t sh7750_mem_readl(void *opaque, hwaddr addr)
switch (addr) { switch (addr) {
case SH7750_BCR1_A7: case SH7750_BCR1_A7:
return s->bcr1; return s->bcr1;
case SH7750_BCR4_A7: case SH7750_BCR4_A7:
if(!has_bcr3_and_bcr4(s)) if(!has_bcr3_and_bcr4(s))
error_access("long read", addr); error_access("long read", addr);
return s->bcr4; return s->bcr4;
case SH7750_WCR1_A7: case SH7750_WCR1_A7:
case SH7750_WCR2_A7: case SH7750_WCR2_A7:
case SH7750_WCR3_A7: case SH7750_WCR3_A7:
@ -288,31 +288,31 @@ static uint32_t sh7750_mem_readl(void *opaque, hwaddr addr)
case SH7750_INTEVT_A7: case SH7750_INTEVT_A7:
return s->cpu->env.intevt; return s->cpu->env.intevt;
case SH7750_CCR_A7: case SH7750_CCR_A7:
return s->ccr; return s->ccr;
case 0x1f000030: /* Processor version */ case 0x1f000030: /* Processor version */
scc = SUPERH_CPU_GET_CLASS(s->cpu); scc = SUPERH_CPU_GET_CLASS(s->cpu);
return scc->pvr; return scc->pvr;
case 0x1f000040: /* Cache version */ case 0x1f000040: /* Cache version */
scc = SUPERH_CPU_GET_CLASS(s->cpu); scc = SUPERH_CPU_GET_CLASS(s->cpu);
return scc->cvr; return scc->cvr;
case 0x1f000044: /* Processor revision */ case 0x1f000044: /* Processor revision */
scc = SUPERH_CPU_GET_CLASS(s->cpu); scc = SUPERH_CPU_GET_CLASS(s->cpu);
return scc->prr; return scc->prr;
default: default:
error_access("long read", addr); error_access("long read", addr);
abort(); abort();
} }
} }
#define is_in_sdrmx(a, x) (a >= SH7750_SDMR ## x ## _A7 \ #define is_in_sdrmx(a, x) (a >= SH7750_SDMR ## x ## _A7 \
&& a <= (SH7750_SDMR ## x ## _A7 + SH7750_SDMR ## x ## _REGNB)) && a <= (SH7750_SDMR ## x ## _A7 + SH7750_SDMR ## x ## _REGNB))
static void sh7750_mem_writeb(void *opaque, hwaddr addr, static void sh7750_mem_writeb(void *opaque, hwaddr addr,
uint32_t mem_value) uint32_t mem_value)
{ {
if (is_in_sdrmx(addr, 2) || is_in_sdrmx(addr, 3)) { if (is_in_sdrmx(addr, 2) || is_in_sdrmx(addr, 3)) {
ignore_access("byte write", addr); ignore_access("byte write", addr);
return; return;
} }
error_access("byte write", addr); error_access("byte write", addr);
@ -320,94 +320,94 @@ static void sh7750_mem_writeb(void *opaque, hwaddr addr,
} }
static void sh7750_mem_writew(void *opaque, hwaddr addr, static void sh7750_mem_writew(void *opaque, hwaddr addr,
uint32_t mem_value) uint32_t mem_value)
{ {
SH7750State *s = opaque; SH7750State *s = opaque;
uint16_t temp; uint16_t temp;
switch (addr) { switch (addr) {
/* SDRAM controller */ /* SDRAM controller */
case SH7750_BCR2_A7: case SH7750_BCR2_A7:
s->bcr2 = mem_value; s->bcr2 = mem_value;
return; return;
case SH7750_BCR3_A7: case SH7750_BCR3_A7:
if(!has_bcr3_and_bcr4(s)) if(!has_bcr3_and_bcr4(s))
error_access("word write", addr); error_access("word write", addr);
s->bcr3 = mem_value; s->bcr3 = mem_value;
return; return;
case SH7750_PCR_A7: case SH7750_PCR_A7:
s->pcr = mem_value; s->pcr = mem_value;
return; return;
case SH7750_RTCNT_A7: case SH7750_RTCNT_A7:
case SH7750_RTCOR_A7: case SH7750_RTCOR_A7:
case SH7750_RTCSR_A7: case SH7750_RTCSR_A7:
ignore_access("word write", addr); ignore_access("word write", addr);
return; return;
/* IO ports */ /* IO ports */
case SH7750_PDTRA_A7: case SH7750_PDTRA_A7:
temp = porta_lines(s); temp = porta_lines(s);
s->pdtra = mem_value; s->pdtra = mem_value;
porta_changed(s, temp); porta_changed(s, temp);
return; return;
case SH7750_PDTRB_A7: case SH7750_PDTRB_A7:
temp = portb_lines(s); temp = portb_lines(s);
s->pdtrb = mem_value; s->pdtrb = mem_value;
portb_changed(s, temp); portb_changed(s, temp);
return; return;
case SH7750_RFCR_A7: case SH7750_RFCR_A7:
fprintf(stderr, "Write access to refresh count register\n"); fprintf(stderr, "Write access to refresh count register\n");
s->rfcr = mem_value; s->rfcr = mem_value;
return; return;
case SH7750_GPIOIC_A7: case SH7750_GPIOIC_A7:
s->gpioic = mem_value; s->gpioic = mem_value;
if (mem_value != 0) { if (mem_value != 0) {
fprintf(stderr, "I/O interrupts not implemented\n"); fprintf(stderr, "I/O interrupts not implemented\n");
abort(); abort();
} }
return; return;
default: default:
error_access("word write", addr); error_access("word write", addr);
abort(); abort();
} }
} }
static void sh7750_mem_writel(void *opaque, hwaddr addr, static void sh7750_mem_writel(void *opaque, hwaddr addr,
uint32_t mem_value) uint32_t mem_value)
{ {
SH7750State *s = opaque; SH7750State *s = opaque;
uint16_t temp; uint16_t temp;
switch (addr) { switch (addr) {
/* SDRAM controller */ /* SDRAM controller */
case SH7750_BCR1_A7: case SH7750_BCR1_A7:
s->bcr1 = mem_value; s->bcr1 = mem_value;
return; return;
case SH7750_BCR4_A7: case SH7750_BCR4_A7:
if(!has_bcr3_and_bcr4(s)) if(!has_bcr3_and_bcr4(s))
error_access("long write", addr); error_access("long write", addr);
s->bcr4 = mem_value; s->bcr4 = mem_value;
return; return;
case SH7750_WCR1_A7: case SH7750_WCR1_A7:
case SH7750_WCR2_A7: case SH7750_WCR2_A7:
case SH7750_WCR3_A7: case SH7750_WCR3_A7:
case SH7750_MCR_A7: case SH7750_MCR_A7:
ignore_access("long write", addr); ignore_access("long write", addr);
return; return;
/* IO ports */ /* IO ports */
case SH7750_PCTRA_A7: case SH7750_PCTRA_A7:
temp = porta_lines(s); temp = porta_lines(s);
s->pctra = mem_value; s->pctra = mem_value;
s->portdira = portdir(mem_value); s->portdira = portdir(mem_value);
s->portpullupa = portpullup(mem_value); s->portpullupa = portpullup(mem_value);
porta_changed(s, temp); porta_changed(s, temp);
return; return;
case SH7750_PCTRB_A7: case SH7750_PCTRB_A7:
temp = portb_lines(s); temp = portb_lines(s);
s->pctrb = mem_value; s->pctrb = mem_value;
s->portdirb = portdir(mem_value); s->portdirb = portdir(mem_value);
s->portpullupb = portpullup(mem_value); s->portpullupb = portpullup(mem_value);
portb_changed(s, temp); portb_changed(s, temp);
return; return;
case SH7750_MMUCR_A7: case SH7750_MMUCR_A7:
if (mem_value & MMUCR_TI) { if (mem_value & MMUCR_TI) {
cpu_sh4_invalidate_tlb(&s->cpu->env); cpu_sh4_invalidate_tlb(&s->cpu->env);
@ -443,10 +443,10 @@ static void sh7750_mem_writel(void *opaque, hwaddr addr,
s->cpu->env.intevt = mem_value & 0x000007ff; s->cpu->env.intevt = mem_value & 0x000007ff;
return; return;
case SH7750_CCR_A7: case SH7750_CCR_A7:
s->ccr = mem_value; s->ccr = mem_value;
return; return;
default: default:
error_access("long write", addr); error_access("long write", addr);
abort(); abort();
} }
} }
@ -496,151 +496,150 @@ static const MemoryRegionOps sh7750_mem_ops = {
*/ */
enum { enum {
UNUSED = 0, UNUSED = 0,
/* interrupt sources */ /* interrupt sources */
IRL_0, IRL_1, IRL_2, IRL_3, IRL_4, IRL_5, IRL_6, IRL_7, IRL_0, IRL_1, IRL_2, IRL_3, IRL_4, IRL_5, IRL_6, IRL_7,
IRL_8, IRL_9, IRL_A, IRL_B, IRL_C, IRL_D, IRL_E, IRL_8, IRL_9, IRL_A, IRL_B, IRL_C, IRL_D, IRL_E,
IRL0, IRL1, IRL2, IRL3, IRL0, IRL1, IRL2, IRL3,
HUDI, GPIOI, HUDI, GPIOI,
DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, DMAC_DMTE3, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, DMAC_DMTE3,
DMAC_DMTE4, DMAC_DMTE5, DMAC_DMTE6, DMAC_DMTE7, DMAC_DMTE4, DMAC_DMTE5, DMAC_DMTE6, DMAC_DMTE7,
DMAC_DMAE, DMAC_DMAE,
PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3, PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3,
TMU3, TMU4, TMU0, TMU1, TMU2_TUNI, TMU2_TICPI, TMU3, TMU4, TMU0, TMU1, TMU2_TUNI, TMU2_TICPI,
RTC_ATI, RTC_PRI, RTC_CUI, RTC_ATI, RTC_PRI, RTC_CUI,
SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI, SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI,
SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI, SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI,
WDT, WDT,
REF_RCMI, REF_ROVI, REF_RCMI, REF_ROVI,
/* interrupt groups */ /* interrupt groups */
DMAC, PCIC1, TMU2, RTC, SCI1, SCIF, REF, DMAC, PCIC1, TMU2, RTC, SCI1, SCIF, REF,
/* irl bundle */ /* irl bundle */
IRL, IRL,
NR_SOURCES, NR_SOURCES,
}; };
static struct intc_vect vectors[] = { static struct intc_vect vectors[] = {
INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620), INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460), INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460),
INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0), INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0),
INTC_VECT(RTC_CUI, 0x4c0), INTC_VECT(RTC_CUI, 0x4c0),
INTC_VECT(SCI1_ERI, 0x4e0), INTC_VECT(SCI1_RXI, 0x500), INTC_VECT(SCI1_ERI, 0x4e0), INTC_VECT(SCI1_RXI, 0x500),
INTC_VECT(SCI1_TXI, 0x520), INTC_VECT(SCI1_TEI, 0x540), INTC_VECT(SCI1_TXI, 0x520), INTC_VECT(SCI1_TEI, 0x540),
INTC_VECT(SCIF_ERI, 0x700), INTC_VECT(SCIF_RXI, 0x720), INTC_VECT(SCIF_ERI, 0x700), INTC_VECT(SCIF_RXI, 0x720),
INTC_VECT(SCIF_BRI, 0x740), INTC_VECT(SCIF_TXI, 0x760), INTC_VECT(SCIF_BRI, 0x740), INTC_VECT(SCIF_TXI, 0x760),
INTC_VECT(WDT, 0x560), INTC_VECT(WDT, 0x560),
INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0), INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0),
}; };
static struct intc_group groups[] = { static struct intc_group groups[] = {
INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI), INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI),
INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI), INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
INTC_GROUP(SCI1, SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI), INTC_GROUP(SCI1, SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI),
INTC_GROUP(SCIF, SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI), INTC_GROUP(SCIF, SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI),
INTC_GROUP(REF, REF_RCMI, REF_ROVI), INTC_GROUP(REF, REF_RCMI, REF_ROVI),
}; };
static struct intc_prio_reg prio_registers[] = { static struct intc_prio_reg prio_registers[] = {
{ 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
{ 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } }, { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } },
{ 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } }, { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } },
{ 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } }, { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
{ 0xfe080000, 0, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0, { 0xfe080000, 0, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0, TMU4, TMU3,
TMU4, TMU3, PCIC1, PCIC0_PCISERR } },
PCIC1, PCIC0_PCISERR } },
}; };
/* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */ /* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */
static struct intc_vect vectors_dma4[] = { static struct intc_vect vectors_dma4[] = {
INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660), INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0), INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
INTC_VECT(DMAC_DMAE, 0x6c0), INTC_VECT(DMAC_DMAE, 0x6c0),
}; };
static struct intc_group groups_dma4[] = { static struct intc_group groups_dma4[] = {
INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
DMAC_DMTE3, DMAC_DMAE), DMAC_DMTE3, DMAC_DMAE),
}; };
/* SH7750R and SH7751R both have 8-channel DMA controllers */ /* SH7750R and SH7751R both have 8-channel DMA controllers */
static struct intc_vect vectors_dma8[] = { static struct intc_vect vectors_dma8[] = {
INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660), INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0), INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
INTC_VECT(DMAC_DMTE4, 0x780), INTC_VECT(DMAC_DMTE5, 0x7a0), INTC_VECT(DMAC_DMTE4, 0x780), INTC_VECT(DMAC_DMTE5, 0x7a0),
INTC_VECT(DMAC_DMTE6, 0x7c0), INTC_VECT(DMAC_DMTE7, 0x7e0), INTC_VECT(DMAC_DMTE6, 0x7c0), INTC_VECT(DMAC_DMTE7, 0x7e0),
INTC_VECT(DMAC_DMAE, 0x6c0), INTC_VECT(DMAC_DMAE, 0x6c0),
}; };
static struct intc_group groups_dma8[] = { static struct intc_group groups_dma8[] = {
INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5, DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5,
DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE), DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE),
}; };
/* SH7750R, SH7751 and SH7751R all have two extra timer channels */ /* SH7750R, SH7751 and SH7751R all have two extra timer channels */
static struct intc_vect vectors_tmu34[] = { static struct intc_vect vectors_tmu34[] = {
INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80), INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80),
}; };
static struct intc_mask_reg mask_registers[] = { static struct intc_mask_reg mask_registers[] = {
{ 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */ { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, TMU4, TMU3, 0, 0, 0, 0, 0, 0, TMU4, TMU3,
PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2,
PCIC1_PCIDMA3, PCIC0_PCISERR } }, PCIC1_PCIDMA3, PCIC0_PCISERR } },
}; };
/* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */ /* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */
static struct intc_vect vectors_irlm[] = { static struct intc_vect vectors_irlm[] = {
INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0), INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360), INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
}; };
/* SH7751 and SH7751R both have PCI */ /* SH7751 and SH7751R both have PCI */
static struct intc_vect vectors_pci[] = { static struct intc_vect vectors_pci[] = {
INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0), INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0),
INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0), INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0),
INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60), INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60),
INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20), INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20),
}; };
static struct intc_group groups_pci[] = { static struct intc_group groups_pci[] = {
INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3), PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3),
}; };
static struct intc_vect vectors_irl[] = { static struct intc_vect vectors_irl[] = {
INTC_VECT(IRL_0, 0x200), INTC_VECT(IRL_0, 0x200),
INTC_VECT(IRL_1, 0x220), INTC_VECT(IRL_1, 0x220),
INTC_VECT(IRL_2, 0x240), INTC_VECT(IRL_2, 0x240),
INTC_VECT(IRL_3, 0x260), INTC_VECT(IRL_3, 0x260),
INTC_VECT(IRL_4, 0x280), INTC_VECT(IRL_4, 0x280),
INTC_VECT(IRL_5, 0x2a0), INTC_VECT(IRL_5, 0x2a0),
INTC_VECT(IRL_6, 0x2c0), INTC_VECT(IRL_6, 0x2c0),
INTC_VECT(IRL_7, 0x2e0), INTC_VECT(IRL_7, 0x2e0),
INTC_VECT(IRL_8, 0x300), INTC_VECT(IRL_8, 0x300),
INTC_VECT(IRL_9, 0x320), INTC_VECT(IRL_9, 0x320),
INTC_VECT(IRL_A, 0x340), INTC_VECT(IRL_A, 0x340),
INTC_VECT(IRL_B, 0x360), INTC_VECT(IRL_B, 0x360),
INTC_VECT(IRL_C, 0x380), INTC_VECT(IRL_C, 0x380),
INTC_VECT(IRL_D, 0x3a0), INTC_VECT(IRL_D, 0x3a0),
INTC_VECT(IRL_E, 0x3c0), INTC_VECT(IRL_E, 0x3c0),
}; };
static struct intc_group groups_irl[] = { static struct intc_group groups_irl[] = {
INTC_GROUP(IRL, IRL_0, IRL_1, IRL_2, IRL_3, IRL_4, IRL_5, IRL_6, INTC_GROUP(IRL, IRL_0, IRL_1, IRL_2, IRL_3, IRL_4, IRL_5, IRL_6,
IRL_7, IRL_8, IRL_9, IRL_A, IRL_B, IRL_C, IRL_D, IRL_E), IRL_7, IRL_8, IRL_9, IRL_A, IRL_B, IRL_C, IRL_D, IRL_E),
}; };
/********************************************************************** /**********************************************************************
@ -679,7 +678,7 @@ static uint64_t sh7750_mmct_read(void *opaque, hwaddr addr,
case MM_ICACHE_ADDR: case MM_ICACHE_ADDR:
case MM_ICACHE_DATA: case MM_ICACHE_DATA:
/* do nothing */ /* do nothing */
break; break;
case MM_ITLB_ADDR: case MM_ITLB_ADDR:
ret = cpu_sh4_read_mmaped_itlb_addr(&s->cpu->env, addr); ret = cpu_sh4_read_mmaped_itlb_addr(&s->cpu->env, addr);
break; break;
@ -689,7 +688,7 @@ static uint64_t sh7750_mmct_read(void *opaque, hwaddr addr,
case MM_OCACHE_ADDR: case MM_OCACHE_ADDR:
case MM_OCACHE_DATA: case MM_OCACHE_DATA:
/* do nothing */ /* do nothing */
break; break;
case MM_UTLB_ADDR: case MM_UTLB_ADDR:
ret = cpu_sh4_read_mmaped_utlb_addr(&s->cpu->env, addr); ret = cpu_sh4_read_mmaped_utlb_addr(&s->cpu->env, addr);
break; break;
@ -722,27 +721,27 @@ static void sh7750_mmct_write(void *opaque, hwaddr addr,
case MM_ICACHE_ADDR: case MM_ICACHE_ADDR:
case MM_ICACHE_DATA: case MM_ICACHE_DATA:
/* do nothing */ /* do nothing */
break; break;
case MM_ITLB_ADDR: case MM_ITLB_ADDR:
cpu_sh4_write_mmaped_itlb_addr(&s->cpu->env, addr, mem_value); cpu_sh4_write_mmaped_itlb_addr(&s->cpu->env, addr, mem_value);
break; break;
case MM_ITLB_DATA: case MM_ITLB_DATA:
cpu_sh4_write_mmaped_itlb_data(&s->cpu->env, addr, mem_value); cpu_sh4_write_mmaped_itlb_data(&s->cpu->env, addr, mem_value);
abort(); abort();
break; break;
case MM_OCACHE_ADDR: case MM_OCACHE_ADDR:
case MM_OCACHE_DATA: case MM_OCACHE_DATA:
/* do nothing */ /* do nothing */
break; break;
case MM_UTLB_ADDR: case MM_UTLB_ADDR:
cpu_sh4_write_mmaped_utlb_addr(&s->cpu->env, addr, mem_value); cpu_sh4_write_mmaped_utlb_addr(&s->cpu->env, addr, mem_value);
break; break;
case MM_UTLB_DATA: case MM_UTLB_DATA:
cpu_sh4_write_mmaped_utlb_data(&s->cpu->env, addr, mem_value); cpu_sh4_write_mmaped_utlb_data(&s->cpu->env, addr, mem_value);
break; break;
default: default:
abort(); abort();
break; break;
} }
} }
@ -758,7 +757,7 @@ SH7750State *sh7750_init(SuperHCPU *cpu, MemoryRegion *sysmem)
s = g_malloc0(sizeof(SH7750State)); s = g_malloc0(sizeof(SH7750State));
s->cpu = cpu; s->cpu = cpu;
s->periph_freq = 60000000; /* 60MHz */ s->periph_freq = 60000000; /* 60MHz */
memory_region_init_io(&s->iomem, NULL, &sh7750_mem_ops, s, memory_region_init_io(&s->iomem, NULL, &sh7750_mem_ops, s,
"memory", 0x1fc01000); "memory", 0x1fc01000);
@ -791,12 +790,12 @@ SH7750State *sh7750_init(SuperHCPU *cpu, MemoryRegion *sysmem)
memory_region_add_subregion(sysmem, 0xf0000000, &s->mmct_iomem); memory_region_add_subregion(sysmem, 0xf0000000, &s->mmct_iomem);
sh_intc_init(sysmem, &s->intc, NR_SOURCES, sh_intc_init(sysmem, &s->intc, NR_SOURCES,
_INTC_ARRAY(mask_registers), _INTC_ARRAY(mask_registers),
_INTC_ARRAY(prio_registers)); _INTC_ARRAY(prio_registers));
sh_intc_register_sources(&s->intc, sh_intc_register_sources(&s->intc,
_INTC_ARRAY(vectors), _INTC_ARRAY(vectors),
_INTC_ARRAY(groups)); _INTC_ARRAY(groups));
cpu->env.intc_handle = &s->intc; cpu->env.intc_handle = &s->intc;
@ -817,50 +816,50 @@ SH7750State *sh7750_init(SuperHCPU *cpu, MemoryRegion *sysmem)
s->intc.irqs[SCIF_BRI]); s->intc.irqs[SCIF_BRI]);
tmu012_init(sysmem, 0x1fd80000, tmu012_init(sysmem, 0x1fd80000,
TMU012_FEAT_TOCR | TMU012_FEAT_3CHAN | TMU012_FEAT_EXTCLK, TMU012_FEAT_TOCR | TMU012_FEAT_3CHAN | TMU012_FEAT_EXTCLK,
s->periph_freq, s->periph_freq,
s->intc.irqs[TMU0], s->intc.irqs[TMU0],
s->intc.irqs[TMU1], s->intc.irqs[TMU1],
s->intc.irqs[TMU2_TUNI], s->intc.irqs[TMU2_TUNI],
s->intc.irqs[TMU2_TICPI]); s->intc.irqs[TMU2_TICPI]);
if (cpu->env.id & (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7751)) { if (cpu->env.id & (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7751)) {
sh_intc_register_sources(&s->intc, sh_intc_register_sources(&s->intc,
_INTC_ARRAY(vectors_dma4), _INTC_ARRAY(vectors_dma4),
_INTC_ARRAY(groups_dma4)); _INTC_ARRAY(groups_dma4));
} }
if (cpu->env.id & (SH_CPU_SH7750R | SH_CPU_SH7751R)) { if (cpu->env.id & (SH_CPU_SH7750R | SH_CPU_SH7751R)) {
sh_intc_register_sources(&s->intc, sh_intc_register_sources(&s->intc,
_INTC_ARRAY(vectors_dma8), _INTC_ARRAY(vectors_dma8),
_INTC_ARRAY(groups_dma8)); _INTC_ARRAY(groups_dma8));
} }
if (cpu->env.id & (SH_CPU_SH7750R | SH_CPU_SH7751 | SH_CPU_SH7751R)) { if (cpu->env.id & (SH_CPU_SH7750R | SH_CPU_SH7751 | SH_CPU_SH7751R)) {
sh_intc_register_sources(&s->intc, sh_intc_register_sources(&s->intc,
_INTC_ARRAY(vectors_tmu34), _INTC_ARRAY(vectors_tmu34),
NULL, 0); NULL, 0);
tmu012_init(sysmem, 0x1e100000, 0, s->periph_freq, tmu012_init(sysmem, 0x1e100000, 0, s->periph_freq,
s->intc.irqs[TMU3], s->intc.irqs[TMU3],
s->intc.irqs[TMU4], s->intc.irqs[TMU4],
NULL, NULL); NULL, NULL);
} }
if (cpu->env.id & (SH_CPU_SH7751_ALL)) { if (cpu->env.id & (SH_CPU_SH7751_ALL)) {
sh_intc_register_sources(&s->intc, sh_intc_register_sources(&s->intc,
_INTC_ARRAY(vectors_pci), _INTC_ARRAY(vectors_pci),
_INTC_ARRAY(groups_pci)); _INTC_ARRAY(groups_pci));
} }
if (cpu->env.id & (SH_CPU_SH7750S | SH_CPU_SH7750R | SH_CPU_SH7751_ALL)) { if (cpu->env.id & (SH_CPU_SH7750S | SH_CPU_SH7750R | SH_CPU_SH7751_ALL)) {
sh_intc_register_sources(&s->intc, sh_intc_register_sources(&s->intc,
_INTC_ARRAY(vectors_irlm), _INTC_ARRAY(vectors_irlm),
NULL, 0); NULL, 0);
} }
sh_intc_register_sources(&s->intc, sh_intc_register_sources(&s->intc,
_INTC_ARRAY(vectors_irl), _INTC_ARRAY(vectors_irl),
_INTC_ARRAY(groups_irl)); _INTC_ARRAY(groups_irl));
return s; return s;
} }

144
hw/sh4/sh7750_regnames.c
View file

@ -12,76 +12,76 @@ typedef struct {
static regname_t regnames[] = { static regname_t regnames[] = {
REGNAME(SH7750_PTEH_A7) REGNAME(SH7750_PTEH_A7)
REGNAME(SH7750_PTEL_A7) REGNAME(SH7750_PTEL_A7)
REGNAME(SH7750_PTEA_A7) REGNAME(SH7750_PTEA_A7)
REGNAME(SH7750_TTB_A7) REGNAME(SH7750_TTB_A7)
REGNAME(SH7750_TEA_A7) REGNAME(SH7750_TEA_A7)
REGNAME(SH7750_MMUCR_A7) REGNAME(SH7750_MMUCR_A7)
REGNAME(SH7750_CCR_A7) REGNAME(SH7750_CCR_A7)
REGNAME(SH7750_QACR0_A7) REGNAME(SH7750_QACR0_A7)
REGNAME(SH7750_QACR1_A7) REGNAME(SH7750_QACR1_A7)
REGNAME(SH7750_TRA_A7) REGNAME(SH7750_TRA_A7)
REGNAME(SH7750_EXPEVT_A7) REGNAME(SH7750_EXPEVT_A7)
REGNAME(SH7750_INTEVT_A7) REGNAME(SH7750_INTEVT_A7)
REGNAME(SH7750_STBCR_A7) REGNAME(SH7750_STBCR_A7)
REGNAME(SH7750_STBCR2_A7) REGNAME(SH7750_STBCR2_A7)
REGNAME(SH7750_FRQCR_A7) REGNAME(SH7750_FRQCR_A7)
REGNAME(SH7750_WTCNT_A7) REGNAME(SH7750_WTCNT_A7)
REGNAME(SH7750_WTCSR_A7) REGNAME(SH7750_WTCSR_A7)
REGNAME(SH7750_R64CNT_A7) REGNAME(SH7750_R64CNT_A7)
REGNAME(SH7750_RSECCNT_A7) REGNAME(SH7750_RSECCNT_A7)
REGNAME(SH7750_RMINCNT_A7) REGNAME(SH7750_RMINCNT_A7)
REGNAME(SH7750_RHRCNT_A7) REGNAME(SH7750_RHRCNT_A7)
REGNAME(SH7750_RWKCNT_A7) REGNAME(SH7750_RWKCNT_A7)
REGNAME(SH7750_RDAYCNT_A7) REGNAME(SH7750_RDAYCNT_A7)
REGNAME(SH7750_RMONCNT_A7) REGNAME(SH7750_RMONCNT_A7)
REGNAME(SH7750_RYRCNT_A7) REGNAME(SH7750_RYRCNT_A7)
REGNAME(SH7750_RSECAR_A7) REGNAME(SH7750_RSECAR_A7)
REGNAME(SH7750_RMINAR_A7) REGNAME(SH7750_RMINAR_A7)
REGNAME(SH7750_RHRAR_A7) REGNAME(SH7750_RHRAR_A7)
REGNAME(SH7750_RWKAR_A7) REGNAME(SH7750_RWKAR_A7)
REGNAME(SH7750_RDAYAR_A7) REGNAME(SH7750_RDAYAR_A7)
REGNAME(SH7750_RMONAR_A7) REGNAME(SH7750_RMONAR_A7)
REGNAME(SH7750_RCR1_A7) REGNAME(SH7750_RCR1_A7)
REGNAME(SH7750_RCR2_A7) REGNAME(SH7750_RCR2_A7)
REGNAME(SH7750_BCR1_A7) REGNAME(SH7750_BCR1_A7)
REGNAME(SH7750_BCR2_A7) REGNAME(SH7750_BCR2_A7)
REGNAME(SH7750_WCR1_A7) REGNAME(SH7750_WCR1_A7)
REGNAME(SH7750_WCR2_A7) REGNAME(SH7750_WCR2_A7)
REGNAME(SH7750_WCR3_A7) REGNAME(SH7750_WCR3_A7)
REGNAME(SH7750_MCR_A7) REGNAME(SH7750_MCR_A7)
REGNAME(SH7750_PCR_A7) REGNAME(SH7750_PCR_A7)
REGNAME(SH7750_RTCSR_A7) REGNAME(SH7750_RTCSR_A7)
REGNAME(SH7750_RTCNT_A7) REGNAME(SH7750_RTCNT_A7)
REGNAME(SH7750_RTCOR_A7) REGNAME(SH7750_RTCOR_A7)
REGNAME(SH7750_RFCR_A7) REGNAME(SH7750_RFCR_A7)
REGNAME(SH7750_SAR0_A7) REGNAME(SH7750_SAR0_A7)
REGNAME(SH7750_SAR1_A7) REGNAME(SH7750_SAR1_A7)
REGNAME(SH7750_SAR2_A7) REGNAME(SH7750_SAR2_A7)
REGNAME(SH7750_SAR3_A7) REGNAME(SH7750_SAR3_A7)
REGNAME(SH7750_DAR0_A7) REGNAME(SH7750_DAR0_A7)
REGNAME(SH7750_DAR1_A7) REGNAME(SH7750_DAR1_A7)
REGNAME(SH7750_DAR2_A7) REGNAME(SH7750_DAR2_A7)
REGNAME(SH7750_DAR3_A7) REGNAME(SH7750_DAR3_A7)
REGNAME(SH7750_DMATCR0_A7) REGNAME(SH7750_DMATCR0_A7)
REGNAME(SH7750_DMATCR1_A7) REGNAME(SH7750_DMATCR1_A7)
REGNAME(SH7750_DMATCR2_A7) REGNAME(SH7750_DMATCR2_A7)
REGNAME(SH7750_DMATCR3_A7) REGNAME(SH7750_DMATCR3_A7)
REGNAME(SH7750_CHCR0_A7) REGNAME(SH7750_CHCR0_A7)
REGNAME(SH7750_CHCR1_A7) REGNAME(SH7750_CHCR1_A7)
REGNAME(SH7750_CHCR2_A7) REGNAME(SH7750_CHCR2_A7)
REGNAME(SH7750_CHCR3_A7) REGNAME(SH7750_CHCR3_A7)
REGNAME(SH7750_DMAOR_A7) REGNAME(SH7750_DMAOR_A7)
REGNAME(SH7750_PCTRA_A7) REGNAME(SH7750_PCTRA_A7)
REGNAME(SH7750_PDTRA_A7) REGNAME(SH7750_PDTRA_A7)
REGNAME(SH7750_PCTRB_A7) REGNAME(SH7750_PCTRB_A7)
REGNAME(SH7750_PDTRB_A7) REGNAME(SH7750_PDTRB_A7)
REGNAME(SH7750_GPIOIC_A7) REGNAME(SH7750_GPIOIC_A7)
REGNAME(SH7750_ICR_A7) REGNAME(SH7750_ICR_A7)
REGNAME(SH7750_BCR3_A7) REGNAME(SH7750_BCR3_A7)
REGNAME(SH7750_BCR4_A7) REGNAME(SH7750_BCR4_A7)
REGNAME(SH7750_SDMR2_A7) REGNAME(SH7750_SDMR2_A7)
REGNAME(SH7750_SDMR3_A7) {(uint32_t) - 1, NULL} REGNAME(SH7750_SDMR3_A7) {(uint32_t) - 1, NULL}
}; };
const char *regname(uint32_t addr) const char *regname(uint32_t addr)
@ -89,8 +89,8 @@ const char *regname(uint32_t addr)
unsigned int i; unsigned int i;
for (i = 0; regnames[i].regaddr != (uint32_t) - 1; i++) { for (i = 0; regnames[i].regaddr != (uint32_t) - 1; i++) {
if (regnames[i].regaddr == addr) if (regnames[i].regaddr == addr)
return regnames[i].regname; return regnames[i].regname;
} }
return "<unknown reg>"; return "<unknown reg>";

1522
hw/sh4/sh7750_regs.h
View file

File diff suppressed because it is too large Load diff

20
include/hw/sh4/sh.h
View file

@ -44,25 +44,25 @@ typedef struct {
uint16_t portbmask_trigger; uint16_t portbmask_trigger;
/* Return 0 if no action was taken */ /* Return 0 if no action was taken */
int (*port_change_cb) (uint16_t porta, uint16_t portb, int (*port_change_cb) (uint16_t porta, uint16_t portb,
uint16_t * periph_pdtra, uint16_t * periph_pdtra,
uint16_t * periph_portdira, uint16_t * periph_portdira,
uint16_t * periph_pdtrb, uint16_t * periph_pdtrb,
uint16_t * periph_portdirb); uint16_t * periph_portdirb);
} sh7750_io_device; } sh7750_io_device;
int sh7750_register_io_device(struct SH7750State *s, int sh7750_register_io_device(struct SH7750State *s,
sh7750_io_device * device); sh7750_io_device * device);
/* sh_serial.c */ /* sh_serial.c */
#define SH_SERIAL_FEAT_SCIF (1 << 0) #define SH_SERIAL_FEAT_SCIF (1 << 0)
void sh_serial_init(MemoryRegion *sysmem, void sh_serial_init(MemoryRegion *sysmem,
hwaddr base, int feat, hwaddr base, int feat,
uint32_t freq, Chardev *chr, uint32_t freq, Chardev *chr,
qemu_irq eri_source, qemu_irq eri_source,
qemu_irq rxi_source, qemu_irq rxi_source,
qemu_irq txi_source, qemu_irq txi_source,
qemu_irq tei_source, qemu_irq tei_source,
qemu_irq bri_source); qemu_irq bri_source);
/* sh7750.c */ /* sh7750.c */
qemu_irq sh7750_irl(struct SH7750State *s); qemu_irq sh7750_irl(struct SH7750State *s);