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qemu-sparc queue

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Merge remote-tracking branch 'remotes/mcayland/tags/qemu-sparc-20210307' into staging

qemu-sparc queue

# gpg: Signature made Sun 07 Mar 2021 12:07:13 GMT
# gpg:                using RSA key CC621AB98E82200D915CC9C45BC2C56FAE0F321F
# gpg:                issuer "mark.cave-ayland@ilande.co.uk"
# gpg: Good signature from "Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>" [full]
# Primary key fingerprint: CC62 1AB9 8E82 200D 915C  C9C4 5BC2 C56F AE0F 321F

* remotes/mcayland/tags/qemu-sparc-20210307: (42 commits)
  esp: add support for unaligned accesses
  esp: implement non-DMA transfers in PDMA mode
  esp: add trivial implementation of the ESP_RFLAGS register
  esp: convert cmdbuf from array to Fifo8
  esp: convert ti_buf from array to Fifo8
  esp: transition to message out phase after SATN and stop command
  esp: add maxlen parameter to get_cmd()
  esp: raise interrupt after every non-DMA byte transferred to the FIFO
  esp: remove old deferred command completion mechanism
  esp: defer command completion interrupt on incoming data transfers
  esp: latch individual bits in ESP_RINTR register
  esp: implement FIFO flush command
  esp: add 4 byte PDMA read and write transfers
  esp: remove pdma_origin from ESPState
  esp: use FIFO for PDMA transfers between initiator and device
  esp: fix PDMA target selection
  esp: rename get_cmd_cb() to esp_select()
  esp: remove CMD pdma_origin
  esp: use in-built TC to determine PDMA transfer length
  esp: use ti_wptr/ti_rptr to manage the current FIFO position for PDMA
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2021-03-09 13:50:35 +00:00
commit b2ae1009d7
8 changed files with 771 additions and 374 deletions
Download patch file Download diff file Expand all files Collapse all files

52
include/hw/scsi/esp.h
View file

@ -3,6 +3,7 @@
#include "hw/scsi/scsi.h"
#include "hw/sysbus.h"
#include "qemu/fifo8.h"
#include "qom/object.h"
/* esp.c */
@ -10,19 +11,17 @@
typedef void (*ESPDMAMemoryReadWriteFunc)(void *opaque, uint8_t *buf, int len);
#define ESP_REGS 16
#define TI_BUFSZ 16
#define ESP_CMDBUF_SZ 32
#define ESP_FIFO_SZ 16
#define ESP_CMDFIFO_SZ 32
typedef struct ESPState ESPState;
enum pdma_origin_id {
PDMA,
TI,
CMD,
ASYNC,
};
#define TYPE_ESP "esp"
OBJECT_DECLARE_SIMPLE_TYPE(ESPState, ESP)
struct ESPState {
DeviceState parent_obj;
uint8_t rregs[ESP_REGS];
uint8_t wregs[ESP_REGS];
qemu_irq irq;
@ -30,24 +29,18 @@ struct ESPState {
uint8_t chip_id;
bool tchi_written;
int32_t ti_size;
uint32_t ti_rptr, ti_wptr;
uint32_t status;
uint32_t deferred_status;
bool deferred_complete;
uint32_t dma;
uint8_t ti_buf[TI_BUFSZ];
Fifo8 fifo;
SCSIBus bus;
SCSIDevice *current_dev;
SCSIRequest *current_req;
uint8_t cmdbuf[ESP_CMDBUF_SZ];
uint32_t cmdlen;
Fifo8 cmdfifo;
uint8_t cmdfifo_cdb_offset;
uint32_t do_cmd;
/* The amount of data left in the current DMA transfer. */
uint32_t dma_left;
/* The size of the current DMA transfer. Zero if no transfer is in
progress. */
uint32_t dma_counter;
bool data_in_ready;
uint8_t ti_cmd;
int dma_enabled;
uint32_t async_len;
@ -57,16 +50,22 @@ struct ESPState {
ESPDMAMemoryReadWriteFunc dma_memory_write;
void *dma_opaque;
void (*dma_cb)(ESPState *s);
uint8_t pdma_buf[32];
int pdma_origin;
uint32_t pdma_len;
uint32_t pdma_start;
uint32_t pdma_cur;
void (*pdma_cb)(ESPState *s);
uint8_t mig_version_id;
/* Legacy fields for vmstate_esp version < 5 */
uint32_t mig_dma_left;
uint32_t mig_deferred_status;
bool mig_deferred_complete;
uint32_t mig_ti_rptr, mig_ti_wptr;
uint8_t mig_ti_buf[ESP_FIFO_SZ];
uint8_t mig_cmdbuf[ESP_CMDFIFO_SZ];
uint32_t mig_cmdlen;
};
#define TYPE_ESP "esp"
OBJECT_DECLARE_SIMPLE_TYPE(SysBusESPState, ESP)
#define TYPE_SYSBUS_ESP "sysbus-esp"
OBJECT_DECLARE_SIMPLE_TYPE(SysBusESPState, SYSBUS_ESP)
struct SysBusESPState {
/*< private >*/
@ -142,6 +141,7 @@ struct SysBusESPState {
#define INTR_RST 0x80
#define SEQ_0 0x0
#define SEQ_MO 0x1
#define SEQ_CD 0x4
#define CFG1_RESREPT 0x40