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EBase is limited to KSEG0/KSEG1 even on 64bit CPUs.

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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2351 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
ths 2007-01-24 18:01:23 +00:00
parent 4de9b249d3
commit b29a0341d7
3 changed files with 6 additions and 21 deletions
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19
target-mips/op.c
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@ -1158,7 +1158,7 @@ void op_mfc0_prid (void)
void op_mfc0_ebase (void)
{
T0 = (int32_t)env->CP0_EBase;
T0 = env->CP0_EBase;
RETURN();
}
@ -1423,7 +1423,7 @@ void op_mtc0_ebase (void)
{
/* vectored interrupts not implemented */
/* Multi-CPU not implemented */
env->CP0_EBase = (int32_t)0x80000000 | (T0 & 0x3FFFF000);
env->CP0_EBase = 0x80000000 | (T0 & 0x3FFFF000);
RETURN();
}
@ -1563,12 +1563,6 @@ void op_dmfc0_epc (void)
RETURN();
}
void op_dmfc0_ebase (void)
{
T0 = env->CP0_EBase;
RETURN();
}
void op_dmfc0_lladdr (void)
{
T0 = env->CP0_LLAddr >> 4;
@ -1627,15 +1621,6 @@ void op_dmtc0_epc (void)
RETURN();
}
void op_dmtc0_ebase (void)
{
/* vectored interrupts not implemented */
/* Multi-CPU not implemented */
/* XXX: 64bit addressing broken */
env->CP0_EBase = (int32_t)0x80000000 | (T0 & 0x3FFFF000);
RETURN();
}
void op_dmtc0_watchlo0 (void)
{
env->CP0_WatchLo = T0;