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ppc patch queue for 2022-04-20
First batch of ppc patches for QEMU 7.1: - skiboot firmware version bump - pseries: add 2M DDW pagesize - pseries: make virtual hypervisor code TCG only - powernv: introduce GPIO lines for PSIHB device - powernv: remove PCIE root bridge LSI - target/ppc: alternative softfloat 128 bit integer support - assorted fixes -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQQX6/+ZI9AYAK8oOBk82cqW3gMxZAUCYmB/ngAKCRA82cqW3gMx ZE10AP4wPeJQ3fxXb5ylVtL4qkJaLWy6VrJBQSKSb5YEA0fhegEA9ZufpnENQePU gZF0eFAQK/DbSnDyvRQVpGcJM0K1UgI= =nVRw -----END PGP SIGNATURE----- Merge tag 'pull-ppc-20220420-2' of https://gitlab.com/danielhb/qemu into staging ppc patch queue for 2022-04-20 First batch of ppc patches for QEMU 7.1: - skiboot firmware version bump - pseries: add 2M DDW pagesize - pseries: make virtual hypervisor code TCG only - powernv: introduce GPIO lines for PSIHB device - powernv: remove PCIE root bridge LSI - target/ppc: alternative softfloat 128 bit integer support - assorted fixes # -----BEGIN PGP SIGNATURE----- # # iHUEABYKAB0WIQQX6/+ZI9AYAK8oOBk82cqW3gMxZAUCYmB/ngAKCRA82cqW3gMx # ZE10AP4wPeJQ3fxXb5ylVtL4qkJaLWy6VrJBQSKSb5YEA0fhegEA9ZufpnENQePU # gZF0eFAQK/DbSnDyvRQVpGcJM0K1UgI= # =nVRw # -----END PGP SIGNATURE----- # gpg: Signature made Wed 20 Apr 2022 02:48:14 PM PDT # gpg: using EDDSA key 17EBFF9923D01800AF2838193CD9CA96DE033164 # gpg: Can't check signature: No public key * tag 'pull-ppc-20220420-2' of https://gitlab.com/danielhb/qemu: (23 commits) hw/ppc: change indentation to spaces from TABs target/ppc: Add two missing register callbacks on POWER10 ppc/pnv: Remove LSI on the PCIE host bridge pcie: Don't try triggering a LSI when not defined ppc/vof: Fix uninitialized string tracing hw/ppc/ppc405_boards: Initialize g_autofree pointer target/ppc: implement xscvqp[su]qz target/ppc: implement xscv[su]qqp softfloat: add float128_to_int128 softfloat: add float128_to_uint128 softfloat: add int128_to_float128 softfloat: add uint128_to_float128 qemu/int128: add int128_urshift target/ppc: Improve KVM hypercall trace spapr: Move nested KVM hypercalls under a TCG only config. spapr: Move hypercall_register_softmmu ppc/pnv: Remove useless checks in set_irq handlers ppc/pnv: Remove PnvPsiClas::irq_set ppc/pnv: Remove PnvOCC::psi link ppc/pnv: Remove PnvLpcController::psi link ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
commit
b1efff6bf0
32 changed files with 446 additions and 137 deletions
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@ -6457,6 +6457,7 @@ static void init_proc_POWER10(CPUPPCState *env)
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register_power5p_common_sprs(env);
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register_power5p_lpar_sprs(env);
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register_power5p_ear_sprs(env);
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register_power5p_tb_sprs(env);
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register_power6_common_sprs(env);
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register_power6_dbg_sprs(env);
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register_power8_tce_address_control_sprs(env);
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@ -6467,6 +6468,7 @@ static void init_proc_POWER10(CPUPPCState *env)
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register_power8_pmu_user_sprs(env);
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register_power8_tm_sprs(env);
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register_power8_pspb_sprs(env);
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register_power8_dpdes_sprs(env);
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register_vtb_sprs(env);
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register_power8_ic_sprs(env);
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register_power8_book4_sprs(env);
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@ -2925,6 +2925,27 @@ VSX_CVT_FP_TO_INT(xvcvspsxws, 4, float32, int32, VsrW(i), VsrW(i), 0x80000000U)
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VSX_CVT_FP_TO_INT(xvcvspuxds, 2, float32, uint64, VsrW(2 * i), VsrD(i), 0ULL)
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VSX_CVT_FP_TO_INT(xvcvspuxws, 4, float32, uint32, VsrW(i), VsrW(i), 0U)
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#define VSX_CVT_FP_TO_INT128(op, tp, rnan) \
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void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
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{ \
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ppc_vsr_t t; \
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int flags; \
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\
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helper_reset_fpstatus(env); \
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t.s128 = float128_to_##tp##_round_to_zero(xb->f128, &env->fp_status); \
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flags = get_float_exception_flags(&env->fp_status); \
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if (unlikely(flags & float_flag_invalid)) { \
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t.VsrD(0) = float_invalid_cvt(env, flags, t.VsrD(0), rnan, 0, GETPC());\
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t.VsrD(1) = -(t.VsrD(0) & 1); \
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} \
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\
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*xt = t; \
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do_float_check_status(env, GETPC()); \
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}
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VSX_CVT_FP_TO_INT128(XSCVQPUQZ, uint128, 0)
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VSX_CVT_FP_TO_INT128(XSCVQPSQZ, int128, 0x8000000000000000ULL);
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/*
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* Likewise, except that the result is duplicated into both subwords.
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* Power ISA v3.1 has Programming Notes for these insns:
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@ -3058,6 +3079,18 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
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VSX_CVT_INT_TO_FP2(xvcvsxdsp, int64, float32)
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VSX_CVT_INT_TO_FP2(xvcvuxdsp, uint64, float32)
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#define VSX_CVT_INT128_TO_FP(op, tp) \
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void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb)\
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{ \
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helper_reset_fpstatus(env); \
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xt->f128 = tp##_to_float128(xb->s128, &env->fp_status); \
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helper_compute_fprf_float128(env, xt->f128); \
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do_float_check_status(env, GETPC()); \
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}
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VSX_CVT_INT128_TO_FP(XSCVUQQP, uint128);
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VSX_CVT_INT128_TO_FP(XSCVSQQP, int128);
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/*
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* VSX_CVT_INT_TO_FP_VECTOR - VSX integer to floating point conversion
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* op - instruction mnemonic
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@ -388,6 +388,10 @@ DEF_HELPER_4(xscvqpsdz, void, env, i32, vsr, vsr)
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DEF_HELPER_4(xscvqpswz, void, env, i32, vsr, vsr)
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DEF_HELPER_4(xscvqpudz, void, env, i32, vsr, vsr)
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DEF_HELPER_4(xscvqpuwz, void, env, i32, vsr, vsr)
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DEF_HELPER_3(XSCVQPUQZ, void, env, vsr, vsr)
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DEF_HELPER_3(XSCVQPSQZ, void, env, vsr, vsr)
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DEF_HELPER_3(XSCVUQQP, void, env, vsr, vsr)
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DEF_HELPER_3(XSCVSQQP, void, env, vsr, vsr)
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DEF_HELPER_3(xscvhpdp, void, env, vsr, vsr)
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DEF_HELPER_4(xscvsdqp, void, env, i32, vsr, vsr)
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DEF_HELPER_3(xscvspdp, void, env, vsr, vsr)
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@ -91,6 +91,9 @@
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@X_tp_a_bp_rc ...... ....0 ra:5 ....0 .......... rc:1 &X_rc rt=%x_frtp rb=%x_frbp
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&X_tb rt rb
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@X_tb ...... rt:5 ..... rb:5 .......... . &X_tb
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&X_tb_rc rt rb rc:bool
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@X_tb_rc ...... rt:5 ..... rb:5 .......... rc:1 &X_tb_rc
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@ -692,6 +695,10 @@ XSCMPGTQP 111111 ..... ..... ..... 0011100100 - @X
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## VSX Binary Floating-Point Convert Instructions
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XSCVQPDP 111111 ..... 10100 ..... 1101000100 . @X_tb_rc
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XSCVQPUQZ 111111 ..... 00000 ..... 1101000100 - @X_tb
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XSCVQPSQZ 111111 ..... 01000 ..... 1101000100 - @X_tb
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XSCVUQQP 111111 ..... 00011 ..... 1101000100 - @X_tb
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XSCVSQQP 111111 ..... 01011 ..... 1101000100 - @X_tb
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XVCVBF16SPN 111100 ..... 10000 ..... 111011011 .. @XX2
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XVCVSPBF16 111100 ..... 10001 ..... 111011011 .. @XX2
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@ -1680,7 +1680,7 @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
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break;
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#if defined(TARGET_PPC64)
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case KVM_EXIT_PAPR_HCALL:
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trace_kvm_handle_papr_hcall();
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trace_kvm_handle_papr_hcall(run->papr_hcall.nr);
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run->papr_hcall.ret = spapr_hypercall(cpu,
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run->papr_hcall.nr,
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run->papr_hcall.args);
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@ -23,7 +23,7 @@ kvm_failed_get_vpa(void) "Warning: Unable to get VPA information from KVM"
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kvm_handle_dcr_write(void) "handle dcr write"
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kvm_handle_dcr_read(void) "handle dcr read"
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kvm_handle_halt(void) "handle halt"
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kvm_handle_papr_hcall(void) "handle PAPR hypercall"
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kvm_handle_papr_hcall(uint64_t hcall) "0x%" PRIx64
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kvm_handle_epr(void) "handle epr"
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kvm_handle_watchdog_expiry(void) "handle watchdog expiry"
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kvm_handle_debug_exception(void) "handle debug exception"
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@ -838,6 +838,28 @@ static bool trans_XSCVQPDP(DisasContext *ctx, arg_X_tb_rc *a)
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return true;
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}
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static bool do_helper_env_X_tb(DisasContext *ctx, arg_X_tb *a,
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void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_ptr))
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{
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TCGv_ptr xt, xb;
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REQUIRE_INSNS_FLAGS2(ctx, ISA310);
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REQUIRE_VSX(ctx);
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xt = gen_avr_ptr(a->rt);
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xb = gen_avr_ptr(a->rb);
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gen_helper(cpu_env, xt, xb);
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tcg_temp_free_ptr(xt);
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tcg_temp_free_ptr(xb);
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return true;
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}
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TRANS(XSCVUQQP, do_helper_env_X_tb, gen_helper_XSCVUQQP)
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TRANS(XSCVSQQP, do_helper_env_X_tb, gen_helper_XSCVSQQP)
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TRANS(XSCVQPUQZ, do_helper_env_X_tb, gen_helper_XSCVQPUQZ)
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TRANS(XSCVQPSQZ, do_helper_env_X_tb, gen_helper_XSCVQPSQZ)
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#define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \
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static void gen_##name(DisasContext *ctx) \
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{ \
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