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target/ppc: Simplify ppc_booke_xlate() part 2

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Merge the code fetch and data access cases in a common switch.

Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
This commit is contained in:
BALATON Zoltan 2024-05-13 01:27:56 +02:00 • committed by Nicholas Piggin
parent aa20e1c8c6
commit b18489b326
1 changed files with 20 additions and 32 deletions
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36
target/ppc/mmu_common.c
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@ -1221,22 +1221,25 @@ static bool ppc_booke_xlate(PowerPCCPU *cpu, vaddr eaddr,
log_cpu_state_mask(CPU_LOG_MMU, cs, 0); log_cpu_state_mask(CPU_LOG_MMU, cs, 0);
env->error_code = 0; env->error_code = 0;
if (ret == -1) {
if (env->mmu_model == POWERPC_MMU_BOOKE206) {
booke206_update_mas_tlb_miss(env, eaddr, access_type, mmu_idx);
}
}
if (access_type == MMU_INST_FETCH) {
switch (ret) { switch (ret) {
case -1: case -1:
/* No matches in page tables or TLB */ /* No matches in page tables or TLB */
cs->exception_index = POWERPC_EXCP_ITLB; if (env->mmu_model == POWERPC_MMU_BOOKE206) {
booke206_update_mas_tlb_miss(env, eaddr, access_type, mmu_idx);
}
cs->exception_index = (access_type == MMU_INST_FETCH) ?
POWERPC_EXCP_ITLB : POWERPC_EXCP_DTLB;
env->spr[SPR_BOOKE_DEAR] = eaddr; env->spr[SPR_BOOKE_DEAR] = eaddr;
env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type); env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
break; break;
case -2: case -2:
/* Access rights violation */ /* Access rights violation */
cs->exception_index = POWERPC_EXCP_ISI; cs->exception_index = (access_type == MMU_INST_FETCH) ?
POWERPC_EXCP_ISI : POWERPC_EXCP_DSI;
if (access_type != MMU_INST_FETCH) {
env->spr[SPR_BOOKE_DEAR] = eaddr;
env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
}
break; break;
case -3: case -3:
/* No execute protection violation */ /* No execute protection violation */
@ -1244,22 +1247,7 @@ static bool ppc_booke_xlate(PowerPCCPU *cpu, vaddr eaddr,
env->spr[SPR_BOOKE_ESR] = 0; env->spr[SPR_BOOKE_ESR] = 0;
break; break;
} }
} else {
switch (ret) {
case -1:
/* No matches in page tables or TLB */
cs->exception_index = POWERPC_EXCP_DTLB;
env->spr[SPR_BOOKE_DEAR] = eaddr;
env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
break;
case -2:
/* Access rights violation */
cs->exception_index = POWERPC_EXCP_DSI;
env->spr[SPR_BOOKE_DEAR] = eaddr;
env->spr[SPR_BOOKE_ESR] = mmubooke206_esr(mmu_idx, access_type);
break;
}
}
return false; return false;
} }