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tcg/arm: Implement add/sub carry opcodes

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Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2025-01-15 23:35:53 +00:00
parent 75351891b8
commit b15c0d11a2
3 changed files with 161 additions and 59 deletions
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4
tcg/arm/tcg-target-con-set.h
View file

@ -31,6 +31,8 @@ C_O1_I2(r, r, rIK)
C_O1_I2(r, r, rIN)
C_O1_I2(r, r, ri)
C_O1_I2(r, rI, r)
C_O1_I2(r, rI, rIK)
C_O1_I2(r, rI, rIN)
C_O1_I2(r, rZ, rZ)
C_O1_I2(w, 0, w)
C_O1_I2(w, w, w)
@ -43,5 +45,3 @@ C_O1_I4(r, r, rIN, rIK, 0)
C_O2_I1(e, p, q)
C_O2_I2(e, p, q, q)
C_O2_I2(r, r, r, r)
C_O2_I4(r, r, r, r, rIN, rIK)
C_O2_I4(r, r, rI, rI, rIN, rIK)

4
tcg/arm/tcg-target-has.h
View file

@ -24,8 +24,8 @@ extern bool use_neon_instructions;
#endif
/* optional instructions */
#define TCG_TARGET_HAS_add2_i32 1
#define TCG_TARGET_HAS_sub2_i32 1
#define TCG_TARGET_HAS_add2_i32 0
#define TCG_TARGET_HAS_sub2_i32 0
#define TCG_TARGET_HAS_qemu_st8_i32 0
#define TCG_TARGET_HAS_qemu_ldst_i128 0

212
tcg/arm/tcg-target.c.inc
View file

@ -178,6 +178,8 @@ typedef enum {
INSN_DMB_ISH = 0xf57ff05b,
INSN_DMB_MCR = 0xee070fba,
INSN_MSRI_CPSR = 0x0360f000,
/* Architected nop introduced in v6k. */
/* ??? This is an MSR (imm) 0,0,0 insn. Anyone know if this
also Just So Happened to do nothing on pre-v6k so that we
@ -1826,21 +1828,74 @@ static const TCGOutOpBinary outop_add = {
.out_rri = tgen_addi,
};
static void tgen_addco(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
tcg_out_dat_reg(s, COND_AL, ARITH_ADD | TO_CPSR,
a0, a1, a2, SHIFT_IMM_LSL(0));
}
static void tgen_addco_imm(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, tcg_target_long a2)
{
tcg_out_dat_IN(s, COND_AL, ARITH_ADD | TO_CPSR, ARITH_SUB | TO_CPSR,
a0, a1, a2);
}
static const TCGOutOpBinary outop_addco = {
.base.static_constraint = C_NotImplemented,
.base.static_constraint = C_O1_I2(r, r, rIN),
.out_rrr = tgen_addco,
.out_rri = tgen_addco_imm,
};
static void tgen_addci(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
tcg_out_dat_reg(s, COND_AL, ARITH_ADC, a0, a1, a2, SHIFT_IMM_LSL(0));
}
static void tgen_addci_imm(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, tcg_target_long a2)
{
tcg_out_dat_IK(s, COND_AL, ARITH_ADC, ARITH_SBC, a0, a1, a2);
}
static const TCGOutOpAddSubCarry outop_addci = {
.base.static_constraint = C_NotImplemented,
.base.static_constraint = C_O1_I2(r, r, rIK),
.out_rrr = tgen_addci,
.out_rri = tgen_addci_imm,
};
static void tgen_addcio(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
tcg_out_dat_reg(s, COND_AL, ARITH_ADC | TO_CPSR,
a0, a1, a2, SHIFT_IMM_LSL(0));
}
static void tgen_addcio_imm(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, tcg_target_long a2)
{
tcg_out_dat_IK(s, COND_AL, ARITH_ADC | TO_CPSR, ARITH_SBC | TO_CPSR,
a0, a1, a2);
}
static const TCGOutOpBinary outop_addcio = {
.base.static_constraint = C_NotImplemented,
.base.static_constraint = C_O1_I2(r, r, rIK),
.out_rrr = tgen_addcio,
.out_rri = tgen_addcio_imm,
};
/* Set C to @c; NZVQ all set to 0. */
static void tcg_out_movi_apsr_c(TCGContext *s, bool c)
{
int imm12 = encode_imm_nofail(c << 29);
tcg_out32(s, (COND_AL << 28) | INSN_MSRI_CPSR | 0x80000 | imm12);
}
static void tcg_out_set_carry(TCGContext *s)
{
g_assert_not_reached();
tcg_out_movi_apsr_c(s, 1);
}
static void tgen_and(TCGContext *s, TCGType type,
@ -2152,21 +2207,115 @@ static const TCGOutOpSubtract outop_sub = {
.out_rir = tgen_subfi,
};
static void tgen_subbo_rrr(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
tcg_out_dat_reg(s, COND_AL, ARITH_SUB | TO_CPSR,
a0, a1, a2, SHIFT_IMM_LSL(0));
}
static void tgen_subbo_rri(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, tcg_target_long a2)
{
tcg_out_dat_IN(s, COND_AL, ARITH_SUB | TO_CPSR, ARITH_ADD | TO_CPSR,
a0, a1, a2);
}
static void tgen_subbo_rir(TCGContext *s, TCGType type,
TCGReg a0, tcg_target_long a1, TCGReg a2)
{
tcg_out_dat_imm(s, COND_AL, ARITH_RSB | TO_CPSR,
a0, a2, encode_imm_nofail(a1));
}
static void tgen_subbo_rii(TCGContext *s, TCGType type,
TCGReg a0, tcg_target_long a1, tcg_target_long a2)
{
tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_TMP, a2);
tgen_subbo_rir(s, TCG_TYPE_I32, a0, a1, TCG_REG_TMP);
}
static const TCGOutOpAddSubCarry outop_subbo = {
.base.static_constraint = C_NotImplemented,
.base.static_constraint = C_O1_I2(r, rI, rIN),
.out_rrr = tgen_subbo_rrr,
.out_rri = tgen_subbo_rri,
.out_rir = tgen_subbo_rir,
.out_rii = tgen_subbo_rii,
};
static void tgen_subbi_rrr(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
tcg_out_dat_reg(s, COND_AL, ARITH_SBC,
a0, a1, a2, SHIFT_IMM_LSL(0));
}
static void tgen_subbi_rri(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, tcg_target_long a2)
{
tcg_out_dat_IK(s, COND_AL, ARITH_SBC, ARITH_ADC, a0, a1, a2);
}
static void tgen_subbi_rir(TCGContext *s, TCGType type,
TCGReg a0, tcg_target_long a1, TCGReg a2)
{
tcg_out_dat_imm(s, COND_AL, ARITH_RSC, a0, a2, encode_imm_nofail(a1));
}
static void tgen_subbi_rii(TCGContext *s, TCGType type,
TCGReg a0, tcg_target_long a1, tcg_target_long a2)
{
tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_TMP, a2);
tgen_subbi_rir(s, TCG_TYPE_I32, a0, a1, TCG_REG_TMP);
}
static const TCGOutOpAddSubCarry outop_subbi = {
.base.static_constraint = C_NotImplemented,
.base.static_constraint = C_O1_I2(r, rI, rIK),
.out_rrr = tgen_subbi_rrr,
.out_rri = tgen_subbi_rri,
.out_rir = tgen_subbi_rir,
.out_rii = tgen_subbi_rii,
};
static void tgen_subbio_rrr(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
{
tcg_out_dat_reg(s, COND_AL, ARITH_SBC | TO_CPSR,
a0, a1, a2, SHIFT_IMM_LSL(0));
}
static void tgen_subbio_rri(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, tcg_target_long a2)
{
tcg_out_dat_IK(s, COND_AL, ARITH_SBC | TO_CPSR, ARITH_ADC | TO_CPSR,
a0, a1, a2);
}
static void tgen_subbio_rir(TCGContext *s, TCGType type,
TCGReg a0, tcg_target_long a1, TCGReg a2)
{
tcg_out_dat_imm(s, COND_AL, ARITH_RSC | TO_CPSR,
a0, a2, encode_imm_nofail(a1));
}
static void tgen_subbio_rii(TCGContext *s, TCGType type,
TCGReg a0, tcg_target_long a1, tcg_target_long a2)
{
tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_TMP, a2);
tgen_subbio_rir(s, TCG_TYPE_I32, a0, a1, TCG_REG_TMP);
}
static const TCGOutOpAddSubCarry outop_subbio = {
.base.static_constraint = C_NotImplemented,
.base.static_constraint = C_O1_I2(r, rI, rIK),
.out_rrr = tgen_subbio_rrr,
.out_rri = tgen_subbio_rri,
.out_rir = tgen_subbio_rir,
.out_rii = tgen_subbio_rii,
};
static void tcg_out_set_borrow(TCGContext *s)
{
g_assert_not_reached();
tcg_out_movi_apsr_c(s, 0); /* borrow = !carry */
}
static void tgen_xor(TCGContext *s, TCGType type,
@ -2369,8 +2518,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
const TCGArg args[TCG_MAX_OP_ARGS],
const int const_args[TCG_MAX_OP_ARGS])
{
TCGArg a0, a1, a2, a3, a4, a5;
switch (opc) {
case INDEX_op_goto_ptr:
tcg_out_b_reg(s, COND_AL, args[0]);
@ -2404,47 +2551,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
tcg_out_st32(s, COND_AL, args[0], args[1], args[2]);
break;
case INDEX_op_add2_i32:
a0 = args[0], a1 = args[1], a2 = args[2];
a3 = args[3], a4 = args[4], a5 = args[5];
if (a0 == a3 || (a0 == a5 && !const_args[5])) {
a0 = TCG_REG_TMP;
}
tcg_out_dat_rIN(s, COND_AL, ARITH_ADD | TO_CPSR, ARITH_SUB | TO_CPSR,
a0, a2, a4, const_args[4]);
tcg_out_dat_rIK(s, COND_AL, ARITH_ADC, ARITH_SBC,
a1, a3, a5, const_args[5]);
tcg_out_mov_reg(s, COND_AL, args[0], a0);
break;
case INDEX_op_sub2_i32:
a0 = args[0], a1 = args[1], a2 = args[2];
a3 = args[3], a4 = args[4], a5 = args[5];
if ((a0 == a3 && !const_args[3]) || (a0 == a5 && !const_args[5])) {
a0 = TCG_REG_TMP;
}
if (const_args[2]) {
if (const_args[4]) {
tcg_out_movi32(s, COND_AL, a0, a4);
a4 = a0;
}
tcg_out_dat_rI(s, COND_AL, ARITH_RSB | TO_CPSR, a0, a4, a2, 1);
} else {
tcg_out_dat_rIN(s, COND_AL, ARITH_SUB | TO_CPSR,
ARITH_ADD | TO_CPSR, a0, a2, a4, const_args[4]);
}
if (const_args[3]) {
if (const_args[5]) {
tcg_out_movi32(s, COND_AL, a1, a5);
a5 = a1;
}
tcg_out_dat_rI(s, COND_AL, ARITH_RSC, a1, a5, a3, 1);
} else {
tcg_out_dat_rIK(s, COND_AL, ARITH_SBC, ARITH_ADC,
a1, a3, a5, const_args[5]);
}
tcg_out_mov_reg(s, COND_AL, args[0], a0);
break;
case INDEX_op_qemu_ld_i32:
tcg_out_qemu_ld(s, args[0], -1, args[1], args[2], TCG_TYPE_I32);
break;
@ -2490,10 +2596,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_st_i32:
return C_O0_I2(r, r);
case INDEX_op_add2_i32:
return C_O2_I4(r, r, r, r, rIN, rIK);
case INDEX_op_sub2_i32:
return C_O2_I4(r, r, rI, rI, rIN, rIK);
case INDEX_op_qemu_ld_i32:
return C_O1_I1(r, q);
case INDEX_op_qemu_ld_i64: