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target/mips: Add basic description of MXU ASE

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Add a comment that contains a basic description of MXU ASE.

Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
This commit is contained in:
Aleksandar Markovic 2018-10-16 13:26:57 +02:00
parent 50e7edc5ac
commit b158d449bb
1 changed files with 20 additions and 0 deletions
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20
target/mips/translate.c
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@ -1389,6 +1389,26 @@ enum {
OPC_BINSRI_df = (0x7 << 23) | OPC_MSA_BIT_09, OPC_BINSRI_df = (0x7 << 23) | OPC_MSA_BIT_09,
}; };
/*
* AN OVERVIEW OF MXU EXTENSION INSTRUCTION SET
* ============================================
*
* MXU (full name: MIPS eXtension/enhanced Unit) is an SIMD extension of MIPS32
* instructions set. It is designed to fit the needs of signal, graphical and
* video processing applications. MXU instruction set is used in Xburst family
* of microprocessors by Ingenic.
*
* MXU unit contains 17 registers called X0-X16. X0 is always zero, and X16 is
* the control register.
*
* Compiled after:
*
* "XBurst® Instruction Set Architecture MIPS eXtension/enhanced Unit
* Programming Manual", Ingenic Semiconductor Co, Ltd., 2017
*/
/* global register indices */ /* global register indices */
static TCGv cpu_gpr[32], cpu_PC; static TCGv cpu_gpr[32], cpu_PC;
static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC]; static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];