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pci, pc, acpi fixes, enhancements
This includes some pretty big changes: - pci master abort support by Marcel - pci IRQ API rework by Marcel - acpi generation support by myself Everything has gone through several revisions, latest versions have been on list for a while without any more comments, tested by several people. Please pull for 1.7. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.15 (GNU/Linux) iQEcBAABAgAGBQJSXNO8AAoJECgfDbjSjVRp7VAH/0B73mCOiyVACGx7fazK3SGK X8TxZWVtG5A77ISqKyrtjLAhK9DCQjEzQTbMNhXHM3Ar6crwo7nJZnQvH2Gh1X2p 34BOQSVc4rtXz5pwDIr48dBLrxeslwXub79chUs+IK1/4RSn3h3nuS3k6JVkmLJN rcHMj4ljJmi4Hd9vOpmS1jo/a61usi36hhU7CMgcrsXzStZycBBzCozOB3VW8p1X /iwyf91YjmNPkn9gA3/aViGjszu8jE91dkA0C+ljwvcGbs2yEl3LCWEJfsMvoh5P 2M+k0XXbHwq/P9PFMa/2/lWOo4EO4Oxa+G/6QvovJrteYnktr+E9DqjU8pCT7yI= =CVfs -----END PGP SIGNATURE----- Merge remote-tracking branch 'mst/tags/for_anthony' into staging pci, pc, acpi fixes, enhancements This includes some pretty big changes: - pci master abort support by Marcel - pci IRQ API rework by Marcel - acpi generation support by myself Everything has gone through several revisions, latest versions have been on list for a while without any more comments, tested by several people. Please pull for 1.7. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Tue 15 Oct 2013 07:33:48 AM CEST using RSA key ID D28D5469 # gpg: Can't check signature: public key not found * mst/tags/for_anthony: (39 commits) ssdt-proc: update generated file ssdt: fix PBLK length i386: ACPI table generation code from seabios pc: use new api to add builtin tables acpi: add interface to access user-installed tables hpet: add API to find it pvpanic: add API to access io port ich9: APIs for pc guest info piix: APIs for pc guest info acpi/piix: add macros for acpi property names i386: define pc guest info loader: allow adding ROMs in done callbacks i386: add bios linker/loader loader: use file path size from fw_cfg.h acpi: ssdt pcihp: updat generated file acpi: pre-compiled ASL files acpi: add rules to compile ASL source i386: add ACPI table files from seabios q35: expose mmcfg size as a property q35: use macro for MCFG property name ... Message-id: 1381818560-18367-1-git-send-email-mst@redhat.com Signed-off-by: Anthony Liguori <anthony@codemonkey.ws>
This commit is contained in:
Anthony Liguori
commit
b0eb759fb2
95 changed files with 16666 additions and 172 deletions
72
hw/pci/pci.c
72
hw/pci/pci.c
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@ -83,7 +83,7 @@ static const TypeInfo pcie_bus_info = {
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static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num);
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static void pci_update_mappings(PCIDevice *d);
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static void pci_set_irq(void *opaque, int irq_num, int level);
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static void pci_irq_handler(void *opaque, int irq_num, int level);
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static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom);
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static void pci_del_option_rom(PCIDevice *pdev);
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@ -161,7 +161,7 @@ void pci_device_deassert_intx(PCIDevice *dev)
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{
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int i;
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for (i = 0; i < PCI_NUM_PINS; ++i) {
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qemu_set_irq(dev->irq[i], 0);
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pci_irq_handler(dev, i, 0);
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}
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}
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@ -283,6 +283,24 @@ const char *pci_root_bus_path(PCIDevice *dev)
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return rootbus->qbus.name;
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}
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static uint64_t master_abort_mem_read(void *opaque, hwaddr addr, unsigned size)
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{
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return -1ULL;
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}
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static void master_abort_mem_write(void *opaque, hwaddr addr, uint64_t val,
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unsigned size)
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{
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}
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static const MemoryRegionOps master_abort_mem_ops = {
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.read = master_abort_mem_read,
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.write = master_abort_mem_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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#define MASTER_ABORT_MEM_PRIORITY INT_MIN
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static void pci_bus_init(PCIBus *bus, DeviceState *parent,
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const char *name,
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MemoryRegion *address_space_mem,
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@ -294,6 +312,14 @@ static void pci_bus_init(PCIBus *bus, DeviceState *parent,
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bus->address_space_mem = address_space_mem;
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bus->address_space_io = address_space_io;
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memory_region_init_io(&bus->master_abort_mem, OBJECT(bus),
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&master_abort_mem_ops, bus, "pci-master-abort",
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memory_region_size(bus->address_space_mem));
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memory_region_add_subregion_overlap(bus->address_space_mem,
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0, &bus->master_abort_mem,
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MASTER_ABORT_MEM_PRIORITY);
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/* host bridge */
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QLIST_INIT(&bus->child);
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@ -863,14 +889,12 @@ static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
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pci_dev->config_read = config_read;
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pci_dev->config_write = config_write;
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bus->devices[devfn] = pci_dev;
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pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS);
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pci_dev->version_id = 2; /* Current pci device vmstate version */
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return pci_dev;
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}
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static void do_pci_unregister_device(PCIDevice *pci_dev)
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{
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qemu_free_irqs(pci_dev->irq);
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pci_dev->bus->devices[pci_dev->devfn] = NULL;
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pci_config_free(pci_dev);
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@ -1175,7 +1199,7 @@ void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
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/* generic PCI irq support */
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/* 0 <= irq_num <= 3. level must be 0 or 1 */
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static void pci_set_irq(void *opaque, int irq_num, int level)
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static void pci_irq_handler(void *opaque, int irq_num, int level)
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{
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PCIDevice *pci_dev = opaque;
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int change;
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@ -1191,6 +1215,24 @@ static void pci_set_irq(void *opaque, int irq_num, int level)
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pci_change_irq_level(pci_dev, irq_num, change);
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}
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static inline int pci_intx(PCIDevice *pci_dev)
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{
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return pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1;
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}
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qemu_irq pci_allocate_irq(PCIDevice *pci_dev)
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{
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int intx = pci_intx(pci_dev);
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return qemu_allocate_irq(pci_irq_handler, pci_dev, intx);
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}
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void pci_set_irq(PCIDevice *pci_dev, int level)
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{
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int intx = pci_intx(pci_dev);
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pci_irq_handler(pci_dev, intx, level);
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}
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/* Special hooks used by device assignment */
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void pci_bus_set_route_irq_fn(PCIBus *bus, pci_route_irq_fn route_intx_to_irq)
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{
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@ -2264,7 +2306,7 @@ static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev, void *opaque)
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Range *range = opaque;
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PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
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uint16_t cmd = pci_get_word(dev->config + PCI_COMMAND);
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int r;
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int i;
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if (!(cmd & PCI_COMMAND_MEMORY)) {
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return;
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@ -2283,17 +2325,21 @@ static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev, void *opaque)
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range_extend(range, &pref_range);
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}
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}
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for (r = 0; r < PCI_NUM_REGIONS; ++r) {
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PCIIORegion *region = &dev->io_regions[r];
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for (i = 0; i < PCI_NUM_REGIONS; ++i) {
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PCIIORegion *r = &dev->io_regions[i];
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Range region_range;
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if (!region->size ||
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(region->type & PCI_BASE_ADDRESS_SPACE_IO) ||
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!(region->type & PCI_BASE_ADDRESS_MEM_TYPE_64)) {
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if (!r->size ||
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(r->type & PCI_BASE_ADDRESS_SPACE_IO) ||
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!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64)) {
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continue;
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}
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region_range.begin = pci_bar_address(dev, i, r->type, r->size);
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region_range.end = region_range.begin + r->size;
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if (region_range.begin == PCI_BAR_UNMAPPED) {
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continue;
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}
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region_range.begin = pci_get_quad(dev->config + pci_bar(dev, r));
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region_range.end = region_range.begin + region->size;
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region_range.begin = MAX(region_range.begin, 0x1ULL << 32);
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@ -187,7 +187,7 @@ static void hotplug_event_notify(PCIDevice *dev)
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} else if (msi_enabled(dev)) {
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msi_notify(dev, pcie_cap_flags_get_vector(dev));
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} else {
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qemu_set_irq(dev->irq[dev->exp.hpev_intx], dev->exp.hpev_notified);
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pci_set_irq(dev, dev->exp.hpev_notified);
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}
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}
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@ -195,7 +195,7 @@ static void hotplug_event_clear(PCIDevice *dev)
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{
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hotplug_event_update_event_status(dev);
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if (!msix_enabled(dev) && !msi_enabled(dev) && !dev->exp.hpev_notified) {
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qemu_set_irq(dev->irq[dev->exp.hpev_intx], 0);
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pci_irq_deassert(dev);
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}
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}
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@ -285,7 +285,7 @@ static void pcie_aer_root_notify(PCIDevice *dev)
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} else if (msi_enabled(dev)) {
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msi_notify(dev, pcie_aer_root_get_vector(dev));
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} else {
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qemu_set_irq(dev->irq[dev->exp.aer_intx], 1);
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pci_irq_assert(dev);
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}
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}
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@ -768,7 +768,7 @@ void pcie_aer_root_write_config(PCIDevice *dev,
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uint32_t root_cmd = pci_get_long(aer_cap + PCI_ERR_ROOT_COMMAND);
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/* 6.2.4.1.2 Interrupt Generation */
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if (!msix_enabled(dev) && !msi_enabled(dev)) {
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qemu_set_irq(dev->irq[dev->exp.aer_intx], !!(root_cmd & enabled_cmd));
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pci_set_irq(dev, !!(root_cmd & enabled_cmd));
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return;
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}
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@ -24,27 +24,6 @@
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#include "hw/pci/pcie_host.h"
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#include "exec/address-spaces.h"
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/*
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* PCI express mmcfig address
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* bit 20 - 28: bus number
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* bit 15 - 19: device number
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* bit 12 - 14: function number
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* bit 0 - 11: offset in configuration space of a given device
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*/
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#define PCIE_MMCFG_SIZE_MAX (1ULL << 28)
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#define PCIE_MMCFG_SIZE_MIN (1ULL << 20)
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#define PCIE_MMCFG_BUS_BIT 20
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#define PCIE_MMCFG_BUS_MASK 0x1ff
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#define PCIE_MMCFG_DEVFN_BIT 12
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#define PCIE_MMCFG_DEVFN_MASK 0xff
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#define PCIE_MMCFG_CONFOFFSET_MASK 0xfff
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#define PCIE_MMCFG_BUS(addr) (((addr) >> PCIE_MMCFG_BUS_BIT) & \
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PCIE_MMCFG_BUS_MASK)
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#define PCIE_MMCFG_DEVFN(addr) (((addr) >> PCIE_MMCFG_DEVFN_BIT) & \
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PCIE_MMCFG_DEVFN_MASK)
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#define PCIE_MMCFG_CONFOFFSET(addr) ((addr) & PCIE_MMCFG_CONFOFFSET_MASK)
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/* a helper function to get a PCIDevice for a given mmconfig address */
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static inline PCIDevice *pcie_dev_find_by_mmcfg_addr(PCIBus *s,
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uint32_t mmcfg_addr)
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@ -104,9 +83,6 @@ static const MemoryRegionOps pcie_mmcfg_ops = {
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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/* pcie_host::base_addr == PCIE_BASE_ADDR_UNMAPPED when it isn't mapped. */
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#define PCIE_BASE_ADDR_UNMAPPED ((hwaddr)-1ULL)
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int pcie_host_init(PCIExpressHost *e)
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{
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e->base_addr = PCIE_BASE_ADDR_UNMAPPED;
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@ -172,7 +172,7 @@ static void shpc_interrupt_update(PCIDevice *d)
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if (msi_enabled(d) && shpc->msi_requested != level)
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msi_notify(d, 0);
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else
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qemu_set_irq(d->irq[0], level);
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pci_set_irq(d, level);
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shpc->msi_requested = level;
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}
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