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https://github.com/Motorhead1991/qemu.git
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use new timer API
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@689 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard
parent
dff38e7b40
commit
b0a21b5334
6 changed files with 331 additions and 81 deletions
172
hw/i8254.c
172
hw/i8254.c
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@ -43,6 +43,8 @@
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#include "cpu.h"
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#include "vl.h"
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//#define DEBUG_PIT
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#define RW_STATE_LSB 0
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#define RW_STATE_MSB 1
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#define RW_STATE_WORD0 2
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@ -52,12 +54,14 @@
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PITChannelState pit_channels[3];
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static void pit_irq_timer_update(PITChannelState *s, int64_t current_time);
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static int pit_get_count(PITChannelState *s)
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{
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uint64_t d;
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int counter;
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d = muldiv64(cpu_get_ticks() - s->count_load_time, PIT_FREQ, ticks_per_sec);
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d = muldiv64(qemu_get_clock(vm_clock) - s->count_load_time, PIT_FREQ, ticks_per_sec);
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switch(s->mode) {
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case 0:
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case 1:
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@ -77,12 +81,12 @@ static int pit_get_count(PITChannelState *s)
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}
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/* get pit output bit */
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int pit_get_out(PITChannelState *s)
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int pit_get_out(PITChannelState *s, int64_t current_time)
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{
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uint64_t d;
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int out;
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d = muldiv64(cpu_get_ticks() - s->count_load_time, PIT_FREQ, ticks_per_sec);
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d = muldiv64(current_time - s->count_load_time, PIT_FREQ, ticks_per_sec);
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switch(s->mode) {
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default:
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case 0:
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@ -108,53 +112,51 @@ int pit_get_out(PITChannelState *s)
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return out;
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}
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/* get the number of 0 to 1 transitions we had since we call this
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function */
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/* XXX: maybe better to use ticks precision to avoid getting edges
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twice if checks are done at very small intervals */
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int pit_get_out_edges(PITChannelState *s)
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/* return -1 if no transition will occur. */
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static int64_t pit_get_next_transition_time(PITChannelState *s,
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int64_t current_time)
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{
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uint64_t d1, d2;
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int64_t ticks;
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int ret, v;
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uint64_t d, next_time, base;
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int period2;
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ticks = cpu_get_ticks();
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d1 = muldiv64(s->count_last_edge_check_time - s->count_load_time,
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PIT_FREQ, ticks_per_sec);
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d2 = muldiv64(ticks - s->count_load_time,
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PIT_FREQ, ticks_per_sec);
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s->count_last_edge_check_time = ticks;
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d = muldiv64(current_time - s->count_load_time, PIT_FREQ, ticks_per_sec);
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switch(s->mode) {
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default:
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case 0:
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if (d1 < s->count && d2 >= s->count)
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ret = 1;
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else
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ret = 0;
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break;
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case 1:
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ret = 0;
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if (d < s->count)
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next_time = s->count;
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else
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return -1;
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break;
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case 2:
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d1 /= s->count;
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d2 /= s->count;
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ret = d2 - d1;
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base = (d / s->count) * s->count;
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if ((d - base) == 0 && d != 0)
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next_time = base + s->count;
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else
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next_time = base + s->count + 1;
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break;
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case 3:
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v = s->count - ((s->count + 1) >> 1);
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d1 = (d1 + v) / s->count;
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d2 = (d2 + v) / s->count;
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ret = d2 - d1;
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base = (d / s->count) * s->count;
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period2 = ((s->count + 1) >> 1);
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if ((d - base) < period2)
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next_time = base + period2;
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else
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next_time = base + s->count;
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break;
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case 4:
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case 5:
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if (d1 < s->count && d2 >= s->count)
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ret = 1;
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if (d < s->count)
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next_time = s->count;
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else if (d == s->count)
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next_time = s->count + 1;
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else
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ret = 0;
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return -1;
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break;
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}
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return ret;
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/* convert to timer units */
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next_time = s->count_load_time + muldiv64(next_time, ticks_per_sec, PIT_FREQ);
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return next_time;
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}
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/* val must be 0 or 1 */
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@ -170,16 +172,16 @@ void pit_set_gate(PITChannelState *s, int val)
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case 5:
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if (s->gate < val) {
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/* restart counting on rising edge */
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s->count_load_time = cpu_get_ticks();
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s->count_last_edge_check_time = s->count_load_time;
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s->count_load_time = qemu_get_clock(vm_clock);
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pit_irq_timer_update(s, s->count_load_time);
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}
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break;
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case 2:
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case 3:
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if (s->gate < val) {
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/* restart counting on rising edge */
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s->count_load_time = cpu_get_ticks();
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s->count_last_edge_check_time = s->count_load_time;
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s->count_load_time = qemu_get_clock(vm_clock);
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pit_irq_timer_update(s, s->count_load_time);
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}
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/* XXX: disable/enable counting */
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break;
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@ -191,14 +193,9 @@ static inline void pit_load_count(PITChannelState *s, int val)
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{
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if (val == 0)
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val = 0x10000;
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s->count_load_time = cpu_get_ticks();
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s->count_last_edge_check_time = s->count_load_time;
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s->count_load_time = qemu_get_clock(vm_clock);
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s->count = val;
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if (s == &pit_channels[0] && val <= pit_min_timer_count) {
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fprintf(stderr,
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"\nWARNING: qemu: on your system, accurate timer emulation is impossible if its frequency is more than %d Hz. If using a 2.6 guest Linux kernel, you must patch asm/param.h to change HZ from 1000 to 100.\n\n",
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PIT_FREQ / pit_min_timer_count);
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}
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pit_irq_timer_update(s, s->count_load_time);
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}
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static void pit_ioport_write(void *opaque, uint32_t addr, uint32_t val)
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@ -222,6 +219,7 @@ static void pit_ioport_write(void *opaque, uint32_t addr, uint32_t val)
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s->mode = (val >> 1) & 7;
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s->bcd = val & 1;
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s->rw_state = access - 1 + RW_STATE_LSB;
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/* XXX: update irq timer ? */
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break;
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}
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} else {
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@ -279,18 +277,100 @@ static uint32_t pit_ioport_read(void *opaque, uint32_t addr)
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return ret;
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}
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void pit_init(int base)
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static void pit_irq_timer_update(PITChannelState *s, int64_t current_time)
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{
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int64_t expire_time;
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int irq_level;
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if (!s->irq_timer)
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return;
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expire_time = pit_get_next_transition_time(s, current_time);
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irq_level = pit_get_out(s, current_time);
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pic_set_irq(s->irq, irq_level);
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#ifdef DEBUG_PIT
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printf("irq_level=%d next_delay=%f\n",
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irq_level,
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(double)(expire_time - current_time) / ticks_per_sec);
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#endif
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s->next_transition_time = expire_time;
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if (expire_time != -1)
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qemu_mod_timer(s->irq_timer, expire_time);
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else
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qemu_del_timer(s->irq_timer);
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}
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static void pit_irq_timer(void *opaque)
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{
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PITChannelState *s = opaque;
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pit_irq_timer_update(s, s->next_transition_time);
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}
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static void pit_save(QEMUFile *f, void *opaque)
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{
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PITChannelState *s;
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int i;
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for(i = 0; i < 3; i++) {
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s = &pit_channels[i];
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qemu_put_be32s(f, &s->count);
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qemu_put_be16s(f, &s->latched_count);
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qemu_put_8s(f, &s->rw_state);
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qemu_put_8s(f, &s->mode);
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qemu_put_8s(f, &s->bcd);
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qemu_put_8s(f, &s->gate);
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qemu_put_be64s(f, &s->count_load_time);
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if (s->irq_timer) {
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qemu_put_be64s(f, &s->next_transition_time);
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qemu_put_timer(f, s->irq_timer);
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}
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}
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}
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static int pit_load(QEMUFile *f, void *opaque, int version_id)
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{
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PITChannelState *s;
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int i;
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if (version_id != 1)
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return -EINVAL;
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for(i = 0; i < 3; i++) {
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s = &pit_channels[i];
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qemu_get_be32s(f, &s->count);
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qemu_get_be16s(f, &s->latched_count);
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qemu_get_8s(f, &s->rw_state);
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qemu_get_8s(f, &s->mode);
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qemu_get_8s(f, &s->bcd);
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qemu_get_8s(f, &s->gate);
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qemu_get_be64s(f, &s->count_load_time);
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if (s->irq_timer) {
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qemu_get_be64s(f, &s->next_transition_time);
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qemu_get_timer(f, s->irq_timer);
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}
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}
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return 0;
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}
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void pit_init(int base, int irq)
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{
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PITChannelState *s;
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int i;
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for(i = 0;i < 3; i++) {
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s = &pit_channels[i];
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if (i == 0) {
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/* the timer 0 is connected to an IRQ */
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s->irq_timer = qemu_new_timer(vm_clock, pit_irq_timer, s);
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s->irq = irq;
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}
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s->mode = 3;
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s->gate = (i != 2);
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pit_load_count(s, 0);
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}
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register_savevm("i8254", base, 1, pit_save, pit_load, NULL);
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register_ioport_write(base, 4, 1, pit_ioport_write, NULL);
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register_ioport_read(base, 3, 1, pit_ioport_read, NULL);
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}
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