mirror of
https://github.com/Motorhead1991/qemu.git
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ppc patch queue 2018-07-03
Here's a last minue pull request before today's soft freeze. Ideally
I would have sent this earlier, but I was waiting for a couple of
extra fixes I knew were close. And the freeze crept up on me, like
always.
Most of the changes here are bugfixes in any case. There are some
cleanups as well, which have been in my staging tree for a little
while. There are a couple of truly new features (some extensions to
the sam460ex platform), but these are low risk, since they only affect
a new and not really stabilized machine type anyway.
Higlights are:
* Mac platform improvements from Mark Cave-Ayland
* Sam460ex improvements from BALATON Zoltan et al.
* XICS interrupt handler cleanups from Cédric Le Goater
* TCG improvements for atomic loads and stores from Richard
Henderson
* Assorted other bugfixes
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Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-3.0-20180703' into staging
ppc patch queue 2018-07-03
Here's a last minue pull request before today's soft freeze. Ideally
I would have sent this earlier, but I was waiting for a couple of
extra fixes I knew were close. And the freeze crept up on me, like
always.
Most of the changes here are bugfixes in any case. There are some
cleanups as well, which have been in my staging tree for a little
while. There are a couple of truly new features (some extensions to
the sam460ex platform), but these are low risk, since they only affect
a new and not really stabilized machine type anyway.
Higlights are:
* Mac platform improvements from Mark Cave-Ayland
* Sam460ex improvements from BALATON Zoltan et al.
* XICS interrupt handler cleanups from Cédric Le Goater
* TCG improvements for atomic loads and stores from Richard
Henderson
* Assorted other bugfixes
# gpg: Signature made Tue 03 Jul 2018 06:55:22 BST
# gpg: using RSA key 6C38CACA20D9B392
# gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>"
# gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>"
# gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>"
# gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>"
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392
* remotes/dgibson/tags/ppc-for-3.0-20180703: (35 commits)
ppc: Include vga cirrus card into the compiling process
target/ppc: Relax reserved bitmask of indexed store instructions
target/ppc: set is_jmp on ppc_tr_breakpoint_check
spapr: compute default value of "hpt-max-page-size" later
target/ppc/kvm: don't pass cpu to kvm_get_smmu_info()
target/ppc/kvm: get rid of kvm_get_fallback_smmu_info()
ppc440_uc: Basic emulation of PPC440 DMA controller
sam460ex: Add RTC device
hw/timer: Add basic M41T80 emulation
ppc4xx_i2c: Rewrite to model hardware more closely
hw/ppc: Give sam46ex its own config option
fpu_helper.c: fix setting FPSCR[FI] bit
target/ppc: Implement the rest of gen_st_atomic
target/ppc: Implement the rest of gen_ld_atomic
target/ppc: Use atomic min/max helpers
target/ppc: Use MO_ALIGN for EXIWX and ECOWX
target/ppc: Split out gen_st_atomic
target/ppc: Split out gen_ld_atomic
target/ppc: Split out gen_load_locked
target/ppc: Tidy gen_conditional_store
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
# Conflicts:
# hw/ppc/spapr.c
This commit is contained in:
Peter Maydell
commit
b07cd3e748
29 changed files with 1308 additions and 728 deletions
|
|
@ -14,7 +14,8 @@ obj-$(CONFIG_PSERIES) += spapr_rtas_ddw.o
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|||
# PowerPC 4xx boards
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obj-y += ppc4xx_devs.o ppc405_uc.o
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obj-$(CONFIG_PPC4XX) += ppc4xx_pci.o ppc405_boards.o
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obj-$(CONFIG_PPC4XX) += ppc440_bamboo.o ppc440_pcix.o ppc440_uc.o sam460ex.o
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obj-$(CONFIG_PPC4XX) += ppc440_bamboo.o ppc440_pcix.o ppc440_uc.o
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obj-$(CONFIG_SAM460EX) += sam460ex.o
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# PReP
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obj-$(CONFIG_PREP) += prep.o
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obj-$(CONFIG_PREP) += prep_systemio.o
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|
|
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|||
|
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@ -406,11 +406,11 @@ static void ppc_core99_init(MachineState *machine)
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adb_bus = qdev_get_child_bus(dev, "adb.0");
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dev = qdev_create(adb_bus, TYPE_ADB_KEYBOARD);
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qdev_prop_set_bit(dev, "disable-direct-reg3-writes", has_pmu);
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qdev_prop_set_bit(dev, "disable-direct-reg3-writes", true);
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qdev_init_nofail(dev);
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dev = qdev_create(adb_bus, TYPE_ADB_MOUSE);
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qdev_prop_set_bit(dev, "disable-direct-reg3-writes", has_pmu);
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qdev_prop_set_bit(dev, "disable-direct-reg3-writes", true);
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qdev_init_nofail(dev);
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}
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|
|
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@ -150,6 +150,7 @@ static void pnv_core_realize(DeviceState *dev, Error **errp)
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if (!chip) {
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error_propagate(errp, local_err);
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error_prepend(errp, "required link 'chip' not found: ");
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return;
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}
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pc->threads = g_new(PowerPCCPU *, cc->nr_threads);
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|
|
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|||
|
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@ -21,6 +21,7 @@ void ppc440_sdram_init(CPUPPCState *env, int nbanks,
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hwaddr *ram_bases, hwaddr *ram_sizes,
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int do_init);
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void ppc4xx_ahb_init(CPUPPCState *env);
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void ppc4xx_dma_init(CPUPPCState *env, int dcr_base);
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void ppc460ex_pcie_init(CPUPPCState *env);
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#endif /* PPC440_H */
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|
|
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@ -13,6 +13,7 @@
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#include "qemu-common.h"
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#include "qemu/error-report.h"
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#include "qapi/error.h"
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#include "qemu/log.h"
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#include "cpu.h"
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#include "hw/hw.h"
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#include "exec/address-spaces.h"
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|
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@ -802,6 +803,227 @@ void ppc4xx_ahb_init(CPUPPCState *env)
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qemu_register_reset(ppc4xx_ahb_reset, ahb);
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}
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/*****************************************************************************/
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/* DMA controller */
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#define DMA0_CR_CE (1 << 31)
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#define DMA0_CR_PW (1 << 26 | 1 << 25)
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#define DMA0_CR_DAI (1 << 24)
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#define DMA0_CR_SAI (1 << 23)
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#define DMA0_CR_DEC (1 << 2)
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enum {
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DMA0_CR = 0x00,
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DMA0_CT,
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DMA0_SAH,
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DMA0_SAL,
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DMA0_DAH,
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DMA0_DAL,
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DMA0_SGH,
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DMA0_SGL,
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DMA0_SR = 0x20,
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DMA0_SGC = 0x23,
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DMA0_SLP = 0x25,
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DMA0_POL = 0x26,
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};
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typedef struct {
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uint32_t cr;
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uint32_t ct;
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uint64_t sa;
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uint64_t da;
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uint64_t sg;
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} PPC4xxDmaChnl;
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typedef struct {
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int base;
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PPC4xxDmaChnl ch[4];
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uint32_t sr;
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} PPC4xxDmaState;
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static uint32_t dcr_read_dma(void *opaque, int dcrn)
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{
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PPC4xxDmaState *dma = opaque;
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uint32_t val = 0;
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int addr = dcrn - dma->base;
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int chnl = addr / 8;
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switch (addr) {
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case 0x00 ... 0x1f:
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switch (addr % 8) {
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case DMA0_CR:
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val = dma->ch[chnl].cr;
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break;
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case DMA0_CT:
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val = dma->ch[chnl].ct;
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break;
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case DMA0_SAH:
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val = dma->ch[chnl].sa >> 32;
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break;
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case DMA0_SAL:
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val = dma->ch[chnl].sa;
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break;
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case DMA0_DAH:
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val = dma->ch[chnl].da >> 32;
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break;
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case DMA0_DAL:
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val = dma->ch[chnl].da;
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break;
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case DMA0_SGH:
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val = dma->ch[chnl].sg >> 32;
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break;
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case DMA0_SGL:
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val = dma->ch[chnl].sg;
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break;
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}
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break;
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||||
case DMA0_SR:
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val = dma->sr;
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break;
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||||
default:
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qemu_log_mask(LOG_UNIMP, "%s: unimplemented register %x (%d, %x)\n",
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__func__, dcrn, chnl, addr);
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}
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return val;
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}
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static void dcr_write_dma(void *opaque, int dcrn, uint32_t val)
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{
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PPC4xxDmaState *dma = opaque;
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int addr = dcrn - dma->base;
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int chnl = addr / 8;
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switch (addr) {
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case 0x00 ... 0x1f:
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switch (addr % 8) {
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case DMA0_CR:
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dma->ch[chnl].cr = val;
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if (val & DMA0_CR_CE) {
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int count = dma->ch[chnl].ct & 0xffff;
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if (count) {
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int width, i, sidx, didx;
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||||
uint8_t *rptr, *wptr;
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hwaddr rlen, wlen;
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sidx = didx = 0;
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width = 1 << ((val & DMA0_CR_PW) >> 25);
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rptr = cpu_physical_memory_map(dma->ch[chnl].sa, &rlen, 0);
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wptr = cpu_physical_memory_map(dma->ch[chnl].da, &wlen, 1);
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if (rptr && wptr) {
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if (!(val & DMA0_CR_DEC) &&
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val & DMA0_CR_SAI && val & DMA0_CR_DAI) {
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/* optimise common case */
|
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memmove(wptr, rptr, count * width);
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sidx = didx = count * width;
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} else {
|
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/* do it the slow way */
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for (sidx = didx = i = 0; i < count; i++) {
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uint64_t v = ldn_le_p(rptr + sidx, width);
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stn_le_p(wptr + didx, width, v);
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if (val & DMA0_CR_SAI) {
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sidx += width;
|
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}
|
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if (val & DMA0_CR_DAI) {
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didx += width;
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||||
}
|
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}
|
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}
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}
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if (wptr) {
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cpu_physical_memory_unmap(wptr, wlen, 1, didx);
|
||||
}
|
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if (wptr) {
|
||||
cpu_physical_memory_unmap(rptr, rlen, 0, sidx);
|
||||
}
|
||||
}
|
||||
}
|
||||
break;
|
||||
case DMA0_CT:
|
||||
dma->ch[chnl].ct = val;
|
||||
break;
|
||||
case DMA0_SAH:
|
||||
dma->ch[chnl].sa &= 0xffffffffULL;
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||||
dma->ch[chnl].sa |= (uint64_t)val << 32;
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||||
break;
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||||
case DMA0_SAL:
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dma->ch[chnl].sa &= 0xffffffff00000000ULL;
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dma->ch[chnl].sa |= val;
|
||||
break;
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||||
case DMA0_DAH:
|
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dma->ch[chnl].da &= 0xffffffffULL;
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||||
dma->ch[chnl].da |= (uint64_t)val << 32;
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||||
break;
|
||||
case DMA0_DAL:
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||||
dma->ch[chnl].da &= 0xffffffff00000000ULL;
|
||||
dma->ch[chnl].da |= val;
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||||
break;
|
||||
case DMA0_SGH:
|
||||
dma->ch[chnl].sg &= 0xffffffffULL;
|
||||
dma->ch[chnl].sg |= (uint64_t)val << 32;
|
||||
break;
|
||||
case DMA0_SGL:
|
||||
dma->ch[chnl].sg &= 0xffffffff00000000ULL;
|
||||
dma->ch[chnl].sg |= val;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case DMA0_SR:
|
||||
dma->sr &= ~val;
|
||||
break;
|
||||
default:
|
||||
qemu_log_mask(LOG_UNIMP, "%s: unimplemented register %x (%d, %x)\n",
|
||||
__func__, dcrn, chnl, addr);
|
||||
}
|
||||
}
|
||||
|
||||
static void ppc4xx_dma_reset(void *opaque)
|
||||
{
|
||||
PPC4xxDmaState *dma = opaque;
|
||||
int dma_base = dma->base;
|
||||
|
||||
memset(dma, 0, sizeof(*dma));
|
||||
dma->base = dma_base;
|
||||
}
|
||||
|
||||
void ppc4xx_dma_init(CPUPPCState *env, int dcr_base)
|
||||
{
|
||||
PPC4xxDmaState *dma;
|
||||
int i;
|
||||
|
||||
dma = g_malloc0(sizeof(*dma));
|
||||
dma->base = dcr_base;
|
||||
qemu_register_reset(&ppc4xx_dma_reset, dma);
|
||||
for (i = 0; i < 4; i++) {
|
||||
ppc_dcr_register(env, dcr_base + i * 8 + DMA0_CR,
|
||||
dma, &dcr_read_dma, &dcr_write_dma);
|
||||
ppc_dcr_register(env, dcr_base + i * 8 + DMA0_CT,
|
||||
dma, &dcr_read_dma, &dcr_write_dma);
|
||||
ppc_dcr_register(env, dcr_base + i * 8 + DMA0_SAH,
|
||||
dma, &dcr_read_dma, &dcr_write_dma);
|
||||
ppc_dcr_register(env, dcr_base + i * 8 + DMA0_SAL,
|
||||
dma, &dcr_read_dma, &dcr_write_dma);
|
||||
ppc_dcr_register(env, dcr_base + i * 8 + DMA0_DAH,
|
||||
dma, &dcr_read_dma, &dcr_write_dma);
|
||||
ppc_dcr_register(env, dcr_base + i * 8 + DMA0_DAL,
|
||||
dma, &dcr_read_dma, &dcr_write_dma);
|
||||
ppc_dcr_register(env, dcr_base + i * 8 + DMA0_SGH,
|
||||
dma, &dcr_read_dma, &dcr_write_dma);
|
||||
ppc_dcr_register(env, dcr_base + i * 8 + DMA0_SGL,
|
||||
dma, &dcr_read_dma, &dcr_write_dma);
|
||||
}
|
||||
ppc_dcr_register(env, dcr_base + DMA0_SR,
|
||||
dma, &dcr_read_dma, &dcr_write_dma);
|
||||
ppc_dcr_register(env, dcr_base + DMA0_SGC,
|
||||
dma, &dcr_read_dma, &dcr_write_dma);
|
||||
ppc_dcr_register(env, dcr_base + DMA0_SLP,
|
||||
dma, &dcr_read_dma, &dcr_write_dma);
|
||||
ppc_dcr_register(env, dcr_base + DMA0_POL,
|
||||
dma, &dcr_read_dma, &dcr_write_dma);
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
/* PCI Express controller */
|
||||
/* FIXME: This is not complete and does not work, only implemented partially
|
||||
|
|
|
|||
|
|
@ -37,6 +37,8 @@
|
|||
#include "hw/i2c/smbus.h"
|
||||
#include "hw/usb/hcd-ehci.h"
|
||||
|
||||
#include <libfdt.h>
|
||||
|
||||
#define BINARY_DEVICE_TREE_FILE "canyonlands.dtb"
|
||||
#define UBOOT_FILENAME "u-boot-sam460-20100605.bin"
|
||||
/* to extract the official U-Boot bin from the updater: */
|
||||
|
|
@ -67,6 +69,10 @@
|
|||
*/
|
||||
|
||||
#define CPU_FREQ 1150000000
|
||||
#define PLB_FREQ 230000000
|
||||
#define OPB_FREQ 115000000
|
||||
#define EBC_FREQ 115000000
|
||||
#define UART_FREQ 11059200
|
||||
#define SDRAM_NR_BANKS 4
|
||||
|
||||
/* FIXME: See u-boot.git 8ac41e, also fix in ppc440_uc.c */
|
||||
|
|
@ -255,6 +261,7 @@ static int sam460ex_load_device_tree(hwaddr addr,
|
|||
void *fdt;
|
||||
uint32_t tb_freq = CPU_FREQ;
|
||||
uint32_t clock_freq = CPU_FREQ;
|
||||
int offset;
|
||||
|
||||
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE);
|
||||
if (!filename) {
|
||||
|
|
@ -308,6 +315,27 @@ static int sam460ex_load_device_tree(hwaddr addr,
|
|||
qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "timebase-frequency",
|
||||
tb_freq);
|
||||
|
||||
/* Remove cpm node if it exists (it is not emulated) */
|
||||
offset = fdt_path_offset(fdt, "/cpm");
|
||||
if (offset >= 0) {
|
||||
fdt_nop_node(fdt, offset);
|
||||
}
|
||||
|
||||
/* set serial port clocks */
|
||||
offset = fdt_node_offset_by_compatible(fdt, -1, "ns16550");
|
||||
while (offset >= 0) {
|
||||
fdt_setprop_cell(fdt, offset, "clock-frequency", UART_FREQ);
|
||||
offset = fdt_node_offset_by_compatible(fdt, offset, "ns16550");
|
||||
}
|
||||
|
||||
/* some more clocks */
|
||||
qemu_fdt_setprop_cell(fdt, "/plb", "clock-frequency",
|
||||
PLB_FREQ);
|
||||
qemu_fdt_setprop_cell(fdt, "/plb/opb", "clock-frequency",
|
||||
OPB_FREQ);
|
||||
qemu_fdt_setprop_cell(fdt, "/plb/opb/ebc", "clock-frequency",
|
||||
EBC_FREQ);
|
||||
|
||||
rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr);
|
||||
g_free(fdt);
|
||||
ret = fdt_size;
|
||||
|
|
@ -457,6 +485,7 @@ static void sam460ex_init(MachineState *machine)
|
|||
object_property_set_bool(OBJECT(dev), true, "realized", NULL);
|
||||
smbus_eeprom_init(i2c[0]->bus, 8, smbus_eeprom_buf, smbus_eeprom_size);
|
||||
g_free(smbus_eeprom_buf);
|
||||
i2c_create_slave(i2c[0]->bus, "m41t80", 0x68);
|
||||
|
||||
dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600800, uic[0][3]);
|
||||
i2c[1] = PPC4xx_I2C(dev);
|
||||
|
|
@ -476,6 +505,9 @@ static void sam460ex_init(MachineState *machine)
|
|||
/* MAL */
|
||||
ppc4xx_mal_init(env, 4, 16, &uic[2][3]);
|
||||
|
||||
/* DMA */
|
||||
ppc4xx_dma_init(env, 0x200);
|
||||
|
||||
/* 256K of L2 cache as memory */
|
||||
ppc4xx_l2sram_init(env);
|
||||
/* FIXME: remove this after fixing l2sram mapping in ppc440_uc.c? */
|
||||
|
|
|
|||
|
|
@ -137,7 +137,7 @@ static ICSState *spapr_ics_create(sPAPRMachineState *spapr,
|
|||
goto error;
|
||||
}
|
||||
|
||||
return ICS_SIMPLE(obj);
|
||||
return ICS_BASE(obj);
|
||||
|
||||
error:
|
||||
error_propagate(errp, local_err);
|
||||
|
|
@ -3962,6 +3962,7 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data)
|
|||
mc->no_parallel = 1;
|
||||
mc->default_boot_order = "";
|
||||
mc->default_ram_size = 512 * MiB;
|
||||
mc->default_display = "std";
|
||||
mc->kvm_type = spapr_kvm_type;
|
||||
machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE);
|
||||
mc->pci_allow_0_address = true;
|
||||
|
|
@ -4095,17 +4096,16 @@ static void spapr_machine_2_12_instance_options(MachineState *machine)
|
|||
static void spapr_machine_2_12_class_options(MachineClass *mc)
|
||||
{
|
||||
sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
|
||||
uint8_t mps;
|
||||
|
||||
spapr_machine_3_0_class_options(mc);
|
||||
SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_12);
|
||||
|
||||
if (kvmppc_hpt_needs_host_contiguous_pages()) {
|
||||
mps = ctz64(qemu_getrampagesize());
|
||||
} else {
|
||||
mps = 34; /* allow everything up to 16GiB, i.e. everything */
|
||||
}
|
||||
smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = mps;
|
||||
/* We depend on kvm_enabled() to choose a default value for the
|
||||
* hpt-max-page-size capability. Of course we can't do it here
|
||||
* because this is too early and the HW accelerator isn't initialzed
|
||||
* yet. Postpone this to machine init (see default_caps_with_cpu()).
|
||||
*/
|
||||
smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0;
|
||||
}
|
||||
|
||||
DEFINE_SPAPR_MACHINE(2_12, "2.12", false);
|
||||
|
|
|
|||
|
|
@ -465,6 +465,19 @@ static sPAPRCapabilities default_caps_with_cpu(sPAPRMachineState *spapr,
|
|||
caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN;
|
||||
}
|
||||
|
||||
/* This is for pseries-2.12 and older */
|
||||
if (smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] == 0) {
|
||||
uint8_t mps;
|
||||
|
||||
if (kvmppc_hpt_needs_host_contiguous_pages()) {
|
||||
mps = ctz64(qemu_getrampagesize());
|
||||
} else {
|
||||
mps = 34; /* allow everything up to 16GiB, i.e. everything */
|
||||
}
|
||||
|
||||
caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = mps;
|
||||
}
|
||||
|
||||
return caps;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue