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SPARC: Emulation of Leon3
Leon3 is an open-source VHDL System-On-Chip, well known in space industry (more information on http://www.gaisler.com). Leon3 is made of multiple components available in the GrLib VHDL library. Three devices are implemented: uart, timers and IRQ manager. You can find code for these peripherals in the grlib_* files. Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Fabien Chouteau
Blue Swirl
parent
8b1e132074
commit
b04d989054
8 changed files with 419 additions and 22 deletions
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@ -1,6 +1,7 @@
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#include "exec.h"
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#include "host-utils.h"
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#include "helper.h"
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#include "sysemu.h"
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//#define DEBUG_MMU
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//#define DEBUG_MXCC
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@ -9,6 +10,7 @@
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//#define DEBUG_ASI
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//#define DEBUG_PCALL
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//#define DEBUG_PSTATE
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//#define DEBUG_CACHE_CONTROL
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#ifdef DEBUG_MMU
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#define DPRINTF_MMU(fmt, ...) \
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@ -36,6 +38,13 @@
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#define DPRINTF_PSTATE(fmt, ...) do {} while (0)
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#endif
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#ifdef DEBUG_CACHE_CONTROL
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#define DPRINTF_CACHE_CONTROL(fmt, ...) \
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do { printf("CACHE_CONTROL: " fmt , ## __VA_ARGS__); } while (0)
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#else
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#define DPRINTF_CACHE_CONTROL(fmt, ...) do {} while (0)
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#endif
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#ifdef TARGET_SPARC64
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#ifndef TARGET_ABI32
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#define AM_CHECK(env1) ((env1)->pstate & PS_AM)
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@ -49,6 +58,27 @@
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#define QT0 (env->qt0)
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#define QT1 (env->qt1)
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/* Leon3 cache control */
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/* Cache control: emulate the behavior of cache control registers but without
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any effect on the emulated */
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#define CACHE_STATE_MASK 0x3
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#define CACHE_DISABLED 0x0
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#define CACHE_FROZEN 0x1
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#define CACHE_ENABLED 0x3
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/* Cache Control register fields */
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#define CACHE_CTRL_IF (1 << 4) /* Instruction Cache Freeze on Interrupt */
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#define CACHE_CTRL_DF (1 << 5) /* Data Cache Freeze on Interrupt */
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#define CACHE_CTRL_DP (1 << 14) /* Data cache flush pending */
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#define CACHE_CTRL_IP (1 << 15) /* Instruction cache flush pending */
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#define CACHE_CTRL_IB (1 << 16) /* Instruction burst fetch */
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#define CACHE_CTRL_FI (1 << 21) /* Flush Instruction cache (Write only) */
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#define CACHE_CTRL_FD (1 << 22) /* Flush Data cache (Write only) */
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#define CACHE_CTRL_DS (1 << 23) /* Data cache snoop enable */
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#if defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
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static void do_unassigned_access(target_ulong addr, int is_write, int is_exec,
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int is_asi, int size);
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@ -294,6 +324,13 @@ void HELPER(raise_exception)(int tt)
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raise_exception(tt);
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}
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void helper_shutdown(void)
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{
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#if !defined(CONFIG_USER_ONLY)
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qemu_system_shutdown_request();
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#endif
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}
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void helper_check_align(target_ulong addr, uint32_t align)
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{
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if (addr & align) {
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@ -1612,6 +1649,103 @@ static void dump_asi(const char *txt, target_ulong addr, int asi, int size,
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#ifndef TARGET_SPARC64
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#ifndef CONFIG_USER_ONLY
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/* Leon3 cache control */
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void leon3_cache_control_int(void)
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{
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uint32_t state = 0;
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if (env->cache_control & CACHE_CTRL_IF) {
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/* Instruction cache state */
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state = env->cache_control & CACHE_STATE_MASK;
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if (state == CACHE_ENABLED) {
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state = CACHE_FROZEN;
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DPRINTF_CACHE_CONTROL("Instruction cache: freeze\n");
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}
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env->cache_control &= ~CACHE_STATE_MASK;
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env->cache_control |= state;
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}
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if (env->cache_control & CACHE_CTRL_DF) {
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/* Data cache state */
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state = (env->cache_control >> 2) & CACHE_STATE_MASK;
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if (state == CACHE_ENABLED) {
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state = CACHE_FROZEN;
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DPRINTF_CACHE_CONTROL("Data cache: freeze\n");
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}
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env->cache_control &= ~(CACHE_STATE_MASK << 2);
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env->cache_control |= (state << 2);
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}
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}
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static void leon3_cache_control_st(target_ulong addr, uint64_t val, int size)
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{
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DPRINTF_CACHE_CONTROL("st addr:%08x, val:%" PRIx64 ", size:%d\n",
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addr, val, size);
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if (size != 4) {
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DPRINTF_CACHE_CONTROL("32bits only\n");
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return;
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}
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switch (addr) {
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case 0x00: /* Cache control */
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/* These values must always be read as zeros */
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val &= ~CACHE_CTRL_FD;
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val &= ~CACHE_CTRL_FI;
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val &= ~CACHE_CTRL_IB;
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val &= ~CACHE_CTRL_IP;
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val &= ~CACHE_CTRL_DP;
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env->cache_control = val;
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break;
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case 0x04: /* Instruction cache configuration */
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case 0x08: /* Data cache configuration */
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/* Read Only */
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break;
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default:
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DPRINTF_CACHE_CONTROL("write unknown register %08x\n", addr);
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break;
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};
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}
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static uint64_t leon3_cache_control_ld(target_ulong addr, int size)
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{
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uint64_t ret = 0;
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if (size != 4) {
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DPRINTF_CACHE_CONTROL("32bits only\n");
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return 0;
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}
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switch (addr) {
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case 0x00: /* Cache control */
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ret = env->cache_control;
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break;
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/* Configuration registers are read and only always keep those
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predefined values */
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case 0x04: /* Instruction cache configuration */
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ret = 0x10220000;
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break;
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case 0x08: /* Data cache configuration */
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ret = 0x18220000;
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break;
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default:
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DPRINTF_CACHE_CONTROL("read unknown register %08x\n", addr);
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break;
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};
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DPRINTF_CACHE_CONTROL("st addr:%08x, ret:%" PRIx64 ", size:%d\n",
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addr, ret, size);
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return ret;
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}
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uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
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{
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uint64_t ret = 0;
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@ -1621,8 +1755,13 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
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helper_check_align(addr, size - 1);
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switch (asi) {
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case 2: /* SuperSparc MXCC registers */
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case 2: /* SuperSparc MXCC registers and Leon3 cache control */
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switch (addr) {
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case 0x00: /* Leon3 Cache Control */
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case 0x08: /* Leon3 Instruction Cache config */
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case 0x0C: /* Leon3 Date Cache config */
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ret = leon3_cache_control_ld(addr, size);
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break;
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case 0x01c00a00: /* MXCC control register */
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if (size == 8)
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ret = env->mxccregs[3];
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@ -1850,8 +1989,14 @@ void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size)
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{
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helper_check_align(addr, size - 1);
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switch(asi) {
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case 2: /* SuperSparc MXCC registers */
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case 2: /* SuperSparc MXCC registers and Leon3 cache control */
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switch (addr) {
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case 0x00: /* Leon3 Cache Control */
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case 0x08: /* Leon3 Instruction Cache config */
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case 0x0C: /* Leon3 Date Cache config */
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leon3_cache_control_st(addr, val, size);
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break;
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case 0x01c00000: /* MXCC stream data register 0 */
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if (size == 8)
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env->mxccdata[0] = val;
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@ -4177,6 +4322,13 @@ void do_interrupt(CPUState *env)
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env->pc = env->tbr;
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env->npc = env->pc + 4;
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env->exception_index = -1;
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#if !defined(CONFIG_USER_ONLY)
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/* IRQ acknowledgment */
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if ((intno & ~15) == TT_EXTINT && env->qemu_irq_ack != NULL) {
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env->qemu_irq_ack(env->irq_manager, intno);
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}
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#endif
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}
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#endif
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