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target/riscv: rvv: Add CHECK arg to GEN_OPFVF_WIDEN_TRANS

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Signed-off-by: Anton Blanchard <antonb@tenstorrent.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
Signed-off-by: Max Chou <max.chou@sifive.com>
Message-ID: <20250408103938.3623486-3-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Cc: qemu-stable@nongnu.org
This commit is contained in:
Anton Blanchard 2025-04-08 18:39:30 +08:00 • committed by Alistair Francis
parent 3e8d1e4a62
commit b0450a101d
1 changed files with 9 additions and 9 deletions
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18
target/riscv/insn_trans/trans_rvv.c.inc
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@ -2687,10 +2687,10 @@ static bool opfvf_widen_check(DisasContext *s, arg_rmrr *a)
} }
/* OPFVF with WIDEN */ /* OPFVF with WIDEN */
#define GEN_OPFVF_WIDEN_TRANS(NAME) \ #define GEN_OPFVF_WIDEN_TRANS(NAME, CHECK) \
static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
{ \ { \
if (opfvf_widen_check(s, a)) { \ if (CHECK(s, a)) { \
uint32_t data = 0; \ uint32_t data = 0; \
static gen_helper_opfvf *const fns[2] = { \ static gen_helper_opfvf *const fns[2] = { \
gen_helper_##NAME##_h, gen_helper_##NAME##_w, \ gen_helper_##NAME##_h, gen_helper_##NAME##_w, \
@ -2706,8 +2706,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
return false; \ return false; \
} }
GEN_OPFVF_WIDEN_TRANS(vfwadd_vf) GEN_OPFVF_WIDEN_TRANS(vfwadd_vf, opfvf_widen_check)
GEN_OPFVF_WIDEN_TRANS(vfwsub_vf) GEN_OPFVF_WIDEN_TRANS(vfwsub_vf, opfvf_widen_check)
static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a) static bool opfwv_widen_check(DisasContext *s, arg_rmrr *a)
{ {
@ -2789,7 +2789,7 @@ GEN_OPFVF_TRANS(vfrdiv_vf, opfvf_check)
/* Vector Widening Floating-Point Multiply */ /* Vector Widening Floating-Point Multiply */
GEN_OPFVV_WIDEN_TRANS(vfwmul_vv, opfvv_widen_check) GEN_OPFVV_WIDEN_TRANS(vfwmul_vv, opfvv_widen_check)
GEN_OPFVF_WIDEN_TRANS(vfwmul_vf) GEN_OPFVF_WIDEN_TRANS(vfwmul_vf, opfvf_widen_check)
/* Vector Single-Width Floating-Point Fused Multiply-Add Instructions */ /* Vector Single-Width Floating-Point Fused Multiply-Add Instructions */
GEN_OPFVV_TRANS(vfmacc_vv, opfvv_check) GEN_OPFVV_TRANS(vfmacc_vv, opfvv_check)
@ -2814,10 +2814,10 @@ GEN_OPFVV_WIDEN_TRANS(vfwmacc_vv, opfvv_widen_check)
GEN_OPFVV_WIDEN_TRANS(vfwnmacc_vv, opfvv_widen_check) GEN_OPFVV_WIDEN_TRANS(vfwnmacc_vv, opfvv_widen_check)
GEN_OPFVV_WIDEN_TRANS(vfwmsac_vv, opfvv_widen_check) GEN_OPFVV_WIDEN_TRANS(vfwmsac_vv, opfvv_widen_check)
GEN_OPFVV_WIDEN_TRANS(vfwnmsac_vv, opfvv_widen_check) GEN_OPFVV_WIDEN_TRANS(vfwnmsac_vv, opfvv_widen_check)
GEN_OPFVF_WIDEN_TRANS(vfwmacc_vf) GEN_OPFVF_WIDEN_TRANS(vfwmacc_vf, opfvf_widen_check)
GEN_OPFVF_WIDEN_TRANS(vfwnmacc_vf) GEN_OPFVF_WIDEN_TRANS(vfwnmacc_vf, opfvf_widen_check)
GEN_OPFVF_WIDEN_TRANS(vfwmsac_vf) GEN_OPFVF_WIDEN_TRANS(vfwmsac_vf, opfvf_widen_check)
GEN_OPFVF_WIDEN_TRANS(vfwnmsac_vf) GEN_OPFVF_WIDEN_TRANS(vfwnmsac_vf, opfvf_widen_check)
/* Vector Floating-Point Square-Root Instruction */ /* Vector Floating-Point Square-Root Instruction */