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target-tricore: Add instructions of RRR1 opcode format, which have 0x43 as first opcode

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Add helpers:
    * madd64_q_ssov: multiply two 32 bit q-format number, add them with a
                     64 bit q-format number and saturate.
    * madd32_q_add_ssov: add two 64 bit q-format numbers and return a 32 bit
                         result.
    * maddr_q_ssov: multiplay two 32 bit q-format numbers, add a 32 bit
                    q-format number and saturate.
    * maddr_q: multiplay two 32 bit q-format numbers and add a 32 bit
               q-format number.

Note: madd instructions in the q format can behave strange, e.g.
0x1 + (0x80000000 * 0x80000000) << 1 for 32 bit signed values does not cause an
overflow on the guest, because all intermediate results should be handled as if
they are indefinitely precise. We handle this by inverting the overflow bit for
all cases: a + (0x80000000 * 0x80000000) << 1.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Bastian Koppelmann 2015-02-03 18:36:53 +00:00
parent 2e430e1cdc
commit b00aa8ecbc
4 changed files with 588 additions and 4 deletions
Download patch file Download diff file Expand all files Collapse all files

8
target-tricore/tricore-opcodes.h
View file

@ -1245,10 +1245,10 @@ enum {
OPC2_32_RRR1_MADDS_Q_64_LL = 0x3d,
OPC2_32_RRR1_MADDS_Q_32_UU = 0x24,
OPC2_32_RRR1_MADDS_Q_64_UU = 0x3c,
OPC2_32_RRR1_MADDR_H_16_UL = 0x1e,
OPC2_32_RRR1_MADDRS_H_16_UL = 0x3e,
OPC2_32_RRR1_MADDR_Q_32_L = 0x07,
OPC2_32_RRR1_MADDR_Q_32_U = 0x06,
OPC2_32_RRR1_MADDR_H_64_UL = 0x1e,
OPC2_32_RRR1_MADDRS_H_64_UL = 0x3e,
OPC2_32_RRR1_MADDR_Q_32_LL = 0x07,
OPC2_32_RRR1_MADDR_Q_32_UU = 0x06,
OPC2_32_RRR1_MADDRS_Q_32_LL = 0x27,
OPC2_32_RRR1_MADDRS_Q_32_UU = 0x26,
};