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hw/intc/aspeed: Support setting different register size

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Currently, the size of the regs array is 0x2000, which is too large. So far,
it only use GICINT128 - GICINT134, and the offsets from 0 to 0x1000 are unused.
To save code size, introduce a new class attribute "reg_size" to set the
different register sizes for the INTC models in AST2700 and add a regs
sub-region in the memory container.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20250307035945.3698802-5-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
This commit is contained in:
Jamin Lin 2025-03-07 11:59:13 +08:00 • committed by Cédric Le Goater
parent 563afea0ae
commit b008465d65
2 changed files with 6 additions and 18 deletions
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2
include/hw/intc/aspeed_intc.h
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@ -16,7 +16,6 @@
#define TYPE_ASPEED_2700_INTC TYPE_ASPEED_INTC "-ast2700"
OBJECT_DECLARE_TYPE(AspeedINTCState, AspeedINTCClass, ASPEED_INTC)
#define ASPEED_INTC_NR_REGS (0x2000 >> 2)
#define ASPEED_INTC_NR_INTS 9
struct AspeedINTCState {
@ -42,6 +41,7 @@ struct AspeedINTCClass {
uint32_t num_lines;
uint32_t num_ints;
uint64_t mem_size;
uint64_t nr_regs;
};
#endif /* ASPEED_INTC_H */