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target/arm: Convert barrier insns to decodetree

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Convert the insns in the "Barriers" instruction class to
decodetree: CLREX, DSB, DMB, ISB and SB.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230602155223.2040685-4-peter.maydell@linaro.org
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
This commit is contained in:
Peter Maydell 2023-06-19 11:20:20 +01:00
parent 7fefc70661
commit afcd5df54c
2 changed files with 46 additions and 53 deletions
Download patch file Download diff file Expand all files Collapse all files

7
target/arm/tcg/a64.decode
View file

@ -181,3 +181,10 @@ ERETA 1101011 0100 11111 00001 m:1 11111 11111 &reta # ERETAA, ERETAB
# that isn't specifically allocated to an instruction must NOP # that isn't specifically allocated to an instruction must NOP
NOP 1101 0101 0000 0011 0010 ---- --- 11111 NOP 1101 0101 0000 0011 0010 ---- --- 11111
} }
# Barriers
CLREX 1101 0101 0000 0011 0011 ---- 010 11111
DSB_DMB 1101 0101 0000 0011 0011 domain:2 types:2 10- 11111
ISB 1101 0101 0000 0011 0011 ---- 110 11111
SB 1101 0101 0000 0011 0011 0000 111 11111

92
target/arm/tcg/translate-a64.c
View file

@ -1812,67 +1812,56 @@ static bool trans_AUTIBSP(DisasContext *s, arg_AUTIBSP *a)
return true; return true;
} }
static void gen_clrex(DisasContext *s, uint32_t insn) static bool trans_CLREX(DisasContext *s, arg_CLREX *a)
{ {
tcg_gen_movi_i64(cpu_exclusive_addr, -1); tcg_gen_movi_i64(cpu_exclusive_addr, -1);
return true;
} }
/* CLREX, DSB, DMB, ISB */ static bool trans_DSB_DMB(DisasContext *s, arg_DSB_DMB *a)
static void handle_sync(DisasContext *s, uint32_t insn,
unsigned int op1, unsigned int op2, unsigned int crm)
{ {
/* We handle DSB and DMB the same way */
TCGBar bar; TCGBar bar;
if (op1 != 3) { switch (a->types) {
unallocated_encoding(s); case 1: /* MBReqTypes_Reads */
return; bar = TCG_BAR_SC | TCG_MO_LD_LD | TCG_MO_LD_ST;
break;
case 2: /* MBReqTypes_Writes */
bar = TCG_BAR_SC | TCG_MO_ST_ST;
break;
default: /* MBReqTypes_All */
bar = TCG_BAR_SC | TCG_MO_ALL;
break;
} }
tcg_gen_mb(bar);
return true;
}
switch (op2) { static bool trans_ISB(DisasContext *s, arg_ISB *a)
case 2: /* CLREX */ {
gen_clrex(s, insn); /*
return; * We need to break the TB after this insn to execute
case 4: /* DSB */ * self-modifying code correctly and also to take
case 5: /* DMB */ * any pending interrupts immediately.
switch (crm & 3) { */
case 1: /* MBReqTypes_Reads */ reset_btype(s);
bar = TCG_BAR_SC | TCG_MO_LD_LD | TCG_MO_LD_ST; gen_goto_tb(s, 0, 4);
break; return true;
case 2: /* MBReqTypes_Writes */ }
bar = TCG_BAR_SC | TCG_MO_ST_ST;
break;
default: /* MBReqTypes_All */
bar = TCG_BAR_SC | TCG_MO_ALL;
break;
}
tcg_gen_mb(bar);
return;
case 6: /* ISB */
/* We need to break the TB after this insn to execute
* a self-modified code correctly and also to take
* any pending interrupts immediately.
*/
reset_btype(s);
gen_goto_tb(s, 0, 4);
return;
case 7: /* SB */ static bool trans_SB(DisasContext *s, arg_SB *a)
if (crm != 0 || !dc_isar_feature(aa64_sb, s)) { {
goto do_unallocated; if (!dc_isar_feature(aa64_sb, s)) {
} return false;
/*
* TODO: There is no speculation barrier opcode for TCG;
* MB and end the TB instead.
*/
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
gen_goto_tb(s, 0, 4);
return;
default:
do_unallocated:
unallocated_encoding(s);
return;
} }
/*
* TODO: There is no speculation barrier opcode for TCG;
* MB and end the TB instead.
*/
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
gen_goto_tb(s, 0, 4);
return true;
} }
static void gen_xaflag(void) static void gen_xaflag(void)
@ -2336,9 +2325,6 @@ static void disas_system(DisasContext *s, uint32_t insn)
return; return;
} }
switch (crn) { switch (crn) {
case 3: /* CLREX, DSB, DMB, ISB */
handle_sync(s, insn, op1, op2, crm);
break;
case 4: /* MSR (immediate) */ case 4: /* MSR (immediate) */
handle_msr_i(s, insn, op1, op2, crm); handle_msr_i(s, insn, op1, op2, crm);
break; break;