motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-03 07:43:54 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

pnv/xive2: Introduce macros to manipulate TIMA addresses

Browse source 
TIMA addresses are somewhat special and are split in several bit
fields with different meanings. This patch describes it and introduce
macros to more easily access the various fields.

Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20230601121331.487207-5-fbarrat@linux.ibm.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
This commit is contained in:
Frederic Barrat 2023-06-01 14:13:30 +02:00 • committed by Daniel Henrique Barboza
parent f0fc1c29a8
commit afca92071f
2 changed files with 23 additions and 7 deletions
Download patch file Download diff file Expand all files Collapse all files

16
include/hw/ppc/xive_regs.h
View file

@ -48,6 +48,22 @@
#define TM_SHIFT 16
/*
* TIMA addresses are 12-bits (4k page).
* The MSB indicates a special op with side effect, which can be
* refined with bit 10 (see below).
* The registers, logically grouped in 4 rings (a quad-word each), are
* defined on the 6 LSBs (offset below 0x40)
* In between, we can add a cache line index from 0...3 (ie, 0, 0x80,
* 0x100, 0x180) to select a specific snooper. Those 'snoop port
* address' bits should be dropped when processing the operations as
* they are all equivalent.
*/
#define TM_ADDRESS_MASK 0xC3F
#define TM_SPECIAL_OP 0x800
#define TM_RING_OFFSET 0x30
#define TM_REG_OFFSET 0x3F
/* TM register offsets */
#define TM_QW0_USER 0x000 /* All rings */
#define TM_QW1_OS 0x010 /* Ring 0..2 */