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target/hppa: Decode d for unit instructions

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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-09-16 20:32:37 -07:00
parent fa8e3bed38
commit af24075333
2 changed files with 19 additions and 20 deletions
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14
target/hppa/insns.decode
View file

@ -59,7 +59,7 @@
# All insns that need to form a virtual address should use this set. # All insns that need to form a virtual address should use this set.
&ldst t b x disp sp m scale size &ldst t b x disp sp m scale size
&rr_cf t r cf &rr_cf_d t r cf d
&rrr_cf t r1 r2 cf &rrr_cf t r1 r2 cf
&rrr_cf_d t r1 r2 cf d &rrr_cf_d t r1 r2 cf d
&rrr_cf_sh t r1 r2 cf sh &rrr_cf_sh t r1 r2 cf sh
@ -72,7 +72,7 @@
# Format definitions # Format definitions
#### ####
@rr_cf ...... r:5 ..... cf:4 ....... t:5 &rr_cf @rr_cf_d ...... r:5 ..... cf:4 ...... d:1 t:5 &rr_cf_d
@rrr_cf ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf @rrr_cf ...... r2:5 r1:5 cf:4 ....... t:5 &rrr_cf
@rrr_cf_d ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d @rrr_cf_d ...... r2:5 r1:5 cf:4 ...... d:1 t:5 &rrr_cf_d
@rrr_cf_sh ...... r2:5 r1:5 cf:4 .... sh:2 . t:5 &rrr_cf_sh @rrr_cf_sh ...... r2:5 r1:5 cf:4 .... sh:2 . t:5 &rrr_cf_sh
@ -156,13 +156,13 @@ andcm 000010 ..... ..... .... 000000 . ..... @rrr_cf_d
and 000010 ..... ..... .... 001000 . ..... @rrr_cf_d and 000010 ..... ..... .... 001000 . ..... @rrr_cf_d
or 000010 ..... ..... .... 001001 . ..... @rrr_cf_d or 000010 ..... ..... .... 001001 . ..... @rrr_cf_d
xor 000010 ..... ..... .... 001010 . ..... @rrr_cf_d xor 000010 ..... ..... .... 001010 . ..... @rrr_cf_d
uxor 000010 ..... ..... .... 001110 0 ..... @rrr_cf uxor 000010 ..... ..... .... 001110 . ..... @rrr_cf_d
ds 000010 ..... ..... .... 010001 0 ..... @rrr_cf ds 000010 ..... ..... .... 010001 0 ..... @rrr_cf
cmpclr 000010 ..... ..... .... 100010 0 ..... @rrr_cf cmpclr 000010 ..... ..... .... 100010 0 ..... @rrr_cf
uaddcm 000010 ..... ..... .... 100110 0 ..... @rrr_cf uaddcm 000010 ..... ..... .... 100110 . ..... @rrr_cf_d
uaddcm_tc 000010 ..... ..... .... 100111 0 ..... @rrr_cf uaddcm_tc 000010 ..... ..... .... 100111 . ..... @rrr_cf_d
dcor 000010 ..... 00000 .... 101110 0 ..... @rr_cf dcor 000010 ..... 00000 .... 101110 . ..... @rr_cf_d
dcor_i 000010 ..... 00000 .... 101111 0 ..... @rr_cf dcor_i 000010 ..... 00000 .... 101111 . ..... @rr_cf_d
add 000010 ..... ..... .... 0110.. - ..... @rrr_cf_sh add 000010 ..... ..... .... 0110.. - ..... @rrr_cf_sh
add_l 000010 ..... ..... .... 1010.. 0 ..... @rrr_cf_sh add_l 000010 ..... ..... .... 1010.. 0 ..... @rrr_cf_sh

25
target/hppa/translate.c
View file

@ -1436,12 +1436,11 @@ static bool do_log_reg(DisasContext *ctx, arg_rrr_cf_d *a,
} }
static void do_unit(DisasContext *ctx, unsigned rt, TCGv_reg in1, static void do_unit(DisasContext *ctx, unsigned rt, TCGv_reg in1,
TCGv_reg in2, unsigned cf, bool is_tc, TCGv_reg in2, unsigned cf, bool d, bool is_tc,
void (*fn)(TCGv_reg, TCGv_reg, TCGv_reg)) void (*fn)(TCGv_reg, TCGv_reg, TCGv_reg))
{ {
TCGv_reg dest; TCGv_reg dest;
DisasCond cond; DisasCond cond;
bool d = false;
if (cf == 0) { if (cf == 0) {
dest = dest_gpr(ctx, rt); dest = dest_gpr(ctx, rt);
@ -2772,7 +2771,7 @@ static bool trans_cmpclr(DisasContext *ctx, arg_rrr_cf *a)
return nullify_end(ctx); return nullify_end(ctx);
} }
static bool trans_uxor(DisasContext *ctx, arg_rrr_cf *a) static bool trans_uxor(DisasContext *ctx, arg_rrr_cf_d *a)
{ {
TCGv_reg tcg_r1, tcg_r2; TCGv_reg tcg_r1, tcg_r2;
@ -2781,11 +2780,11 @@ static bool trans_uxor(DisasContext *ctx, arg_rrr_cf *a)
} }
tcg_r1 = load_gpr(ctx, a->r1); tcg_r1 = load_gpr(ctx, a->r1);
tcg_r2 = load_gpr(ctx, a->r2); tcg_r2 = load_gpr(ctx, a->r2);
do_unit(ctx, a->t, tcg_r1, tcg_r2, a->cf, false, tcg_gen_xor_reg); do_unit(ctx, a->t, tcg_r1, tcg_r2, a->cf, a->d, false, tcg_gen_xor_reg);
return nullify_end(ctx); return nullify_end(ctx);
} }
static bool do_uaddcm(DisasContext *ctx, arg_rrr_cf *a, bool is_tc) static bool do_uaddcm(DisasContext *ctx, arg_rrr_cf_d *a, bool is_tc)
{ {
TCGv_reg tcg_r1, tcg_r2, tmp; TCGv_reg tcg_r1, tcg_r2, tmp;
@ -2796,21 +2795,21 @@ static bool do_uaddcm(DisasContext *ctx, arg_rrr_cf *a, bool is_tc)
tcg_r2 = load_gpr(ctx, a->r2); tcg_r2 = load_gpr(ctx, a->r2);
tmp = tcg_temp_new(); tmp = tcg_temp_new();
tcg_gen_not_reg(tmp, tcg_r2); tcg_gen_not_reg(tmp, tcg_r2);
do_unit(ctx, a->t, tcg_r1, tmp, a->cf, is_tc, tcg_gen_add_reg); do_unit(ctx, a->t, tcg_r1, tmp, a->cf, a->d, is_tc, tcg_gen_add_reg);
return nullify_end(ctx); return nullify_end(ctx);
} }
static bool trans_uaddcm(DisasContext *ctx, arg_rrr_cf *a) static bool trans_uaddcm(DisasContext *ctx, arg_rrr_cf_d *a)
{ {
return do_uaddcm(ctx, a, false); return do_uaddcm(ctx, a, false);
} }
static bool trans_uaddcm_tc(DisasContext *ctx, arg_rrr_cf *a) static bool trans_uaddcm_tc(DisasContext *ctx, arg_rrr_cf_d *a)
{ {
return do_uaddcm(ctx, a, true); return do_uaddcm(ctx, a, true);
} }
static bool do_dcor(DisasContext *ctx, arg_rr_cf *a, bool is_i) static bool do_dcor(DisasContext *ctx, arg_rr_cf_d *a, bool is_i)
{ {
TCGv_reg tmp; TCGv_reg tmp;
@ -2821,19 +2820,19 @@ static bool do_dcor(DisasContext *ctx, arg_rr_cf *a, bool is_i)
if (!is_i) { if (!is_i) {
tcg_gen_not_reg(tmp, tmp); tcg_gen_not_reg(tmp, tmp);
} }
tcg_gen_andi_reg(tmp, tmp, 0x11111111); tcg_gen_andi_reg(tmp, tmp, (target_ureg)0x1111111111111111ull);
tcg_gen_muli_reg(tmp, tmp, 6); tcg_gen_muli_reg(tmp, tmp, 6);
do_unit(ctx, a->t, load_gpr(ctx, a->r), tmp, a->cf, false, do_unit(ctx, a->t, load_gpr(ctx, a->r), tmp, a->cf, a->d, false,
is_i ? tcg_gen_add_reg : tcg_gen_sub_reg); is_i ? tcg_gen_add_reg : tcg_gen_sub_reg);
return nullify_end(ctx); return nullify_end(ctx);
} }
static bool trans_dcor(DisasContext *ctx, arg_rr_cf *a) static bool trans_dcor(DisasContext *ctx, arg_rr_cf_d *a)
{ {
return do_dcor(ctx, a, false); return do_dcor(ctx, a, false);
} }
static bool trans_dcor_i(DisasContext *ctx, arg_rr_cf *a) static bool trans_dcor_i(DisasContext *ctx, arg_rr_cf_d *a)
{ {
return do_dcor(ctx, a, true); return do_dcor(ctx, a, true);
} }