motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-03 07:43:54 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

target/riscv: move 128-bit check to TCG realize

Browse source 
Besides removing non-declarative code in instance_init, this also fixes
an issue with query-cpu-model-expansion.  Just invoking it for the
x-rv128 CPU model causes QEMU to exit immediately.  With this patch it
is possible to do

  {'execute': 'query-cpu-model-expansion',
   'arguments':{'type': 'full', 'model': {'name': 'x-rv128'}}}

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini 2025-02-06 14:54:50 +01:00
parent 4044f46978
commit aeb7969cba
2 changed files with 9 additions and 7 deletions
Download patch file Download diff file Expand all files Collapse all files

7
target/riscv/cpu.c
View file

@ -700,13 +700,6 @@ static void rv128_base_cpu_init(Object *obj)
RISCVCPU *cpu = RISCV_CPU(obj); RISCVCPU *cpu = RISCV_CPU(obj);
CPURISCVState *env = &cpu->env; CPURISCVState *env = &cpu->env;
if (qemu_tcg_mttcg_enabled()) {
/* Missing 128-bit aligned atomics */
error_report("128-bit RISC-V currently does not work with Multi "
"Threaded TCG. Please use: -accel tcg,thread=single");
exit(EXIT_FAILURE);
}
cpu->cfg.mmu = true; cpu->cfg.mmu = true;
cpu->cfg.pmp = true; cpu->cfg.pmp = true;

9
target/riscv/tcg/tcg-cpu.c
View file

@ -1014,6 +1014,7 @@ static bool riscv_cpu_is_generic(Object *cpu_obj)
static bool riscv_tcg_cpu_realize(CPUState *cs, Error **errp) static bool riscv_tcg_cpu_realize(CPUState *cs, Error **errp)
{ {
RISCVCPU *cpu = RISCV_CPU(cs); RISCVCPU *cpu = RISCV_CPU(cs);
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
if (!riscv_cpu_tcg_compatible(cpu)) { if (!riscv_cpu_tcg_compatible(cpu)) {
g_autofree char *name = riscv_cpu_get_name(cpu); g_autofree char *name = riscv_cpu_get_name(cpu);
@ -1022,6 +1023,14 @@ static bool riscv_tcg_cpu_realize(CPUState *cs, Error **errp)
return false; return false;
} }
if (mcc->misa_mxl_max >= MXL_RV128 && qemu_tcg_mttcg_enabled()) {
/* Missing 128-bit aligned atomics */
error_setg(errp,
"128-bit RISC-V currently does not work with Multi "
"Threaded TCG. Please use: -accel tcg,thread=single");
return false;
}
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
CPURISCVState *env = &cpu->env; CPURISCVState *env = &cpu->env;