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ppc/pnv: add a PSI bridge class model

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To ease the introduction of the PSI bridge model for POWER9, abstract
the POWER chip differences in a PnvPsi class model and introduce a
specific Pnv8Psi type for POWER8. POWER8 interface to the interrupt
controller is still XICS whereas POWER9 uses the new XIVE model.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20190307223548.20516-2-clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Cédric Le Goater 2019-03-07 23:35:34 +01:00 • committed by David Gibson
parent 31bc6fa7fa
commit ae85605531
4 changed files with 87 additions and 29 deletions
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2
include/hw/ppc/pnv.h
View file

@ -71,7 +71,7 @@ typedef struct Pnv8Chip {
MemoryRegion icp_mmio;
PnvLpcController lpc;
PnvPsi psi;
Pnv8Psi psi;
PnvOCC occ;
} Pnv8Chip;

29
include/hw/ppc/pnv_psi.h
View file

@ -39,7 +39,6 @@ typedef struct PnvPsi {
uint64_t fsp_bar;
/* Interrupt generation */
ICSState ics;
qemu_irq *qirqs;
/* Registers */
@ -48,6 +47,32 @@ typedef struct PnvPsi {
MemoryRegion xscom_regs;
} PnvPsi;
#define TYPE_PNV8_PSI TYPE_PNV_PSI "-POWER8"
#define PNV8_PSI(obj) \
OBJECT_CHECK(Pnv8Psi, (obj), TYPE_PNV8_PSI)
typedef struct Pnv8Psi {
PnvPsi parent;
ICSState ics;
} Pnv8Psi;
#define PNV_PSI_CLASS(klass) \
OBJECT_CLASS_CHECK(PnvPsiClass, (klass), TYPE_PNV_PSI)
#define PNV_PSI_GET_CLASS(obj) \
OBJECT_GET_CLASS(PnvPsiClass, (obj), TYPE_PNV_PSI)
typedef struct PnvPsiClass {
SysBusDeviceClass parent_class;
int chip_type;
uint32_t xscom_pcba;
uint32_t xscom_size;
uint64_t bar_mask;
void (*irq_set)(PnvPsi *psi, int, bool state);
} PnvPsiClass;
/* The PSI and FSP interrupts are muxed on the same IRQ number */
typedef enum PnvPsiIrq {
PSIHB_IRQ_PSI, /* internal use only */
@ -61,6 +86,6 @@ typedef enum PnvPsiIrq {
#define PSI_NUM_INTERRUPTS 6
extern void pnv_psi_irq_set(PnvPsi *psi, PnvPsiIrq irq, bool state);
void pnv_psi_irq_set(PnvPsi *psi, int irq, bool state);
#endif /* _PPC_PNV_PSI_H */