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hw/cxl: Multi-Region CXL Type-3 Devices (Volatile and Persistent)

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This commit enables each CXL Type-3 device to contain one volatile
memory region and one persistent region.

Two new properties have been added to cxl-type3 device initialization:
    [volatile-memdev] and [persistent-memdev]

The existing [memdev] property has been deprecated and will default the
memory region to a persistent memory region (although a user may assign
the region to a ram or file backed region). It cannot be used in
combination with the new [persistent-memdev] property.

Partitioning volatile memory from persistent memory is not yet supported.

Volatile memory is mapped at DPA(0x0), while Persistent memory is mapped
at DPA(vmem->size), per CXL Spec 8.2.9.8.2.0 - Get Partition Info.

Signed-off-by: Gregory Price <gregory.price@memverge.com>
Reviewed-by: Davidlohr Bueso <dave@stgolabs.net>
Reviewed-by: Fan Ni <fan.ni@samsung.com>
Tested-by: Fan Ni <fan.ni@samsung.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

Message-Id: <20230421160827.2227-4-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Gregory Price 2023-04-21 17:08:27 +01:00 • committed by Michael S. Tsirkin
parent 3521176526
commit adacc814f5
7 changed files with 371 additions and 119 deletions
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8
tests/qtest/bios-tables-test.c
View file

@ -1867,13 +1867,13 @@ static void test_acpi_q35_cxl(void)
" -device pxb-cxl,bus_nr=12,bus=pcie.0,id=cxl.1"
" -device pxb-cxl,bus_nr=222,bus=pcie.0,id=cxl.2"
" -device cxl-rp,port=0,bus=cxl.1,id=rp1,chassis=0,slot=2"
" -device cxl-type3,bus=rp1,memdev=cxl-mem1,lsa=lsa1"
" -device cxl-type3,bus=rp1,persistent-memdev=cxl-mem1,lsa=lsa1"
" -device cxl-rp,port=1,bus=cxl.1,id=rp2,chassis=0,slot=3"
" -device cxl-type3,bus=rp2,memdev=cxl-mem2,lsa=lsa2"
" -device cxl-type3,bus=rp2,persistent-memdev=cxl-mem2,lsa=lsa2"
" -device cxl-rp,port=0,bus=cxl.2,id=rp3,chassis=0,slot=5"
" -device cxl-type3,bus=rp3,memdev=cxl-mem3,lsa=lsa3"
" -device cxl-type3,bus=rp3,persistent-memdev=cxl-mem3,lsa=lsa3"
" -device cxl-rp,port=1,bus=cxl.2,id=rp4,chassis=0,slot=6"
" -device cxl-type3,bus=rp4,memdev=cxl-mem4,lsa=lsa4"
" -device cxl-type3,bus=rp4,persistent-memdev=cxl-mem4,lsa=lsa4"
" -M cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.size=4G,cxl-fmw.0.interleave-granularity=8k,"
"cxl-fmw.1.targets.0=cxl.1,cxl-fmw.1.targets.1=cxl.2,cxl-fmw.1.size=4G,cxl-fmw.1.interleave-granularity=8k",
tmp_path, tmp_path, tmp_path, tmp_path,