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tcg/tci: Rename tci_read_r to tci_read_rval

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In the next patches, we want to use tci_read_r to return
the raw register number.  So rename the existing function,
which returns the register value, to tci_read_rval.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2021-01-31 13:25:23 -10:00
parent dbcbda2cd8
commit adaa9a2f9a
1 changed files with 96 additions and 96 deletions
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192
tcg/tci.c
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@ -119,7 +119,7 @@ static uint64_t tci_read_i64(const uint8_t **tb_ptr)
/* Read indexed register (native size) from bytecode. */ /* Read indexed register (native size) from bytecode. */
static tcg_target_ulong static tcg_target_ulong
tci_read_r(const tcg_target_ulong *regs, const uint8_t **tb_ptr) tci_read_rval(const tcg_target_ulong *regs, const uint8_t **tb_ptr)
{ {
tcg_target_ulong value = tci_read_reg(regs, **tb_ptr); tcg_target_ulong value = tci_read_reg(regs, **tb_ptr);
*tb_ptr += 1; *tb_ptr += 1;
@ -131,15 +131,15 @@ tci_read_r(const tcg_target_ulong *regs, const uint8_t **tb_ptr)
static uint64_t tci_read_r64(const tcg_target_ulong *regs, static uint64_t tci_read_r64(const tcg_target_ulong *regs,
const uint8_t **tb_ptr) const uint8_t **tb_ptr)
{ {
uint32_t low = tci_read_r(regs, tb_ptr); uint32_t low = tci_read_rval(regs, tb_ptr);
return tci_uint64(tci_read_r(regs, tb_ptr), low); return tci_uint64(tci_read_rval(regs, tb_ptr), low);
} }
#elif TCG_TARGET_REG_BITS == 64 #elif TCG_TARGET_REG_BITS == 64
/* Read indexed register (64 bit) from bytecode. */ /* Read indexed register (64 bit) from bytecode. */
static uint64_t tci_read_r64(const tcg_target_ulong *regs, static uint64_t tci_read_r64(const tcg_target_ulong *regs,
const uint8_t **tb_ptr) const uint8_t **tb_ptr)
{ {
return tci_read_r(regs, tb_ptr); return tci_read_rval(regs, tb_ptr);
} }
#endif #endif
@ -147,9 +147,9 @@ static uint64_t tci_read_r64(const tcg_target_ulong *regs,
static target_ulong static target_ulong
tci_read_ulong(const tcg_target_ulong *regs, const uint8_t **tb_ptr) tci_read_ulong(const tcg_target_ulong *regs, const uint8_t **tb_ptr)
{ {
target_ulong taddr = tci_read_r(regs, tb_ptr); target_ulong taddr = tci_read_rval(regs, tb_ptr);
#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
taddr += (uint64_t)tci_read_r(regs, tb_ptr) << 32; taddr += (uint64_t)tci_read_rval(regs, tb_ptr) << 32;
#endif #endif
return taddr; return taddr;
} }
@ -365,8 +365,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
continue; continue;
case INDEX_op_setcond_i32: case INDEX_op_setcond_i32:
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr); t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_r(regs, &tb_ptr); t2 = tci_read_rval(regs, &tb_ptr);
condition = *tb_ptr++; condition = *tb_ptr++;
tci_write_reg(regs, t0, tci_compare32(t1, t2, condition)); tci_write_reg(regs, t0, tci_compare32(t1, t2, condition));
break; break;
@ -381,15 +381,15 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
#elif TCG_TARGET_REG_BITS == 64 #elif TCG_TARGET_REG_BITS == 64
case INDEX_op_setcond_i64: case INDEX_op_setcond_i64:
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr); t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_r(regs, &tb_ptr); t2 = tci_read_rval(regs, &tb_ptr);
condition = *tb_ptr++; condition = *tb_ptr++;
tci_write_reg(regs, t0, tci_compare64(t1, t2, condition)); tci_write_reg(regs, t0, tci_compare64(t1, t2, condition));
break; break;
#endif #endif
CASE_32_64(mov) CASE_32_64(mov)
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr); t1 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, t1); tci_write_reg(regs, t0, t1);
break; break;
case INDEX_op_tci_movi_i32: case INDEX_op_tci_movi_i32:
@ -402,51 +402,51 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
CASE_32_64(ld8u) CASE_32_64(ld8u)
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr); t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_s32(&tb_ptr); t2 = tci_read_s32(&tb_ptr);
tci_write_reg(regs, t0, *(uint8_t *)(t1 + t2)); tci_write_reg(regs, t0, *(uint8_t *)(t1 + t2));
break; break;
CASE_32_64(ld8s) CASE_32_64(ld8s)
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr); t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_s32(&tb_ptr); t2 = tci_read_s32(&tb_ptr);
tci_write_reg(regs, t0, *(int8_t *)(t1 + t2)); tci_write_reg(regs, t0, *(int8_t *)(t1 + t2));
break; break;
CASE_32_64(ld16u) CASE_32_64(ld16u)
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr); t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_s32(&tb_ptr); t2 = tci_read_s32(&tb_ptr);
tci_write_reg(regs, t0, *(uint16_t *)(t1 + t2)); tci_write_reg(regs, t0, *(uint16_t *)(t1 + t2));
break; break;
CASE_32_64(ld16s) CASE_32_64(ld16s)
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr); t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_s32(&tb_ptr); t2 = tci_read_s32(&tb_ptr);
tci_write_reg(regs, t0, *(int16_t *)(t1 + t2)); tci_write_reg(regs, t0, *(int16_t *)(t1 + t2));
break; break;
case INDEX_op_ld_i32: case INDEX_op_ld_i32:
CASE_64(ld32u) CASE_64(ld32u)
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr); t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_s32(&tb_ptr); t2 = tci_read_s32(&tb_ptr);
tci_write_reg(regs, t0, *(uint32_t *)(t1 + t2)); tci_write_reg(regs, t0, *(uint32_t *)(t1 + t2));
break; break;
CASE_32_64(st8) CASE_32_64(st8)
t0 = tci_read_r(regs, &tb_ptr); t0 = tci_read_rval(regs, &tb_ptr);
t1 = tci_read_r(regs, &tb_ptr); t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_s32(&tb_ptr); t2 = tci_read_s32(&tb_ptr);
*(uint8_t *)(t1 + t2) = t0; *(uint8_t *)(t1 + t2) = t0;
break; break;
CASE_32_64(st16) CASE_32_64(st16)
t0 = tci_read_r(regs, &tb_ptr); t0 = tci_read_rval(regs, &tb_ptr);
t1 = tci_read_r(regs, &tb_ptr); t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_s32(&tb_ptr); t2 = tci_read_s32(&tb_ptr);
*(uint16_t *)(t1 + t2) = t0; *(uint16_t *)(t1 + t2) = t0;
break; break;
case INDEX_op_st_i32: case INDEX_op_st_i32:
CASE_64(st32) CASE_64(st32)
t0 = tci_read_r(regs, &tb_ptr); t0 = tci_read_rval(regs, &tb_ptr);
t1 = tci_read_r(regs, &tb_ptr); t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_s32(&tb_ptr); t2 = tci_read_s32(&tb_ptr);
*(uint32_t *)(t1 + t2) = t0; *(uint32_t *)(t1 + t2) = t0;
break; break;
@ -455,38 +455,38 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
CASE_32_64(add) CASE_32_64(add)
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr); t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_r(regs, &tb_ptr); t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 + t2); tci_write_reg(regs, t0, t1 + t2);
break; break;
CASE_32_64(sub) CASE_32_64(sub)
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr); t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_r(regs, &tb_ptr); t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 - t2); tci_write_reg(regs, t0, t1 - t2);
break; break;
CASE_32_64(mul) CASE_32_64(mul)
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr); t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_r(regs, &tb_ptr); t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 * t2); tci_write_reg(regs, t0, t1 * t2);
break; break;
CASE_32_64(and) CASE_32_64(and)
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr); t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_r(regs, &tb_ptr); t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 & t2); tci_write_reg(regs, t0, t1 & t2);
break; break;
CASE_32_64(or) CASE_32_64(or)
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr); t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_r(regs, &tb_ptr); t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 | t2); tci_write_reg(regs, t0, t1 | t2);
break; break;
CASE_32_64(xor) CASE_32_64(xor)
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr); t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_r(regs, &tb_ptr); t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 ^ t2); tci_write_reg(regs, t0, t1 ^ t2);
break; break;
@ -494,26 +494,26 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
case INDEX_op_div_i32: case INDEX_op_div_i32:
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr); t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_r(regs, &tb_ptr); t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, (int32_t)t1 / (int32_t)t2); tci_write_reg(regs, t0, (int32_t)t1 / (int32_t)t2);
break; break;
case INDEX_op_divu_i32: case INDEX_op_divu_i32:
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr); t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_r(regs, &tb_ptr); t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, (uint32_t)t1 / (uint32_t)t2); tci_write_reg(regs, t0, (uint32_t)t1 / (uint32_t)t2);
break; break;
case INDEX_op_rem_i32: case INDEX_op_rem_i32:
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr); t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_r(regs, &tb_ptr); t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, (int32_t)t1 % (int32_t)t2); tci_write_reg(regs, t0, (int32_t)t1 % (int32_t)t2);
break; break;
case INDEX_op_remu_i32: case INDEX_op_remu_i32:
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr); t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_r(regs, &tb_ptr); t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, (uint32_t)t1 % (uint32_t)t2); tci_write_reg(regs, t0, (uint32_t)t1 % (uint32_t)t2);
break; break;
@ -521,41 +521,41 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
case INDEX_op_shl_i32: case INDEX_op_shl_i32:
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr); t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_r(regs, &tb_ptr); t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, (uint32_t)t1 << (t2 & 31)); tci_write_reg(regs, t0, (uint32_t)t1 << (t2 & 31));
break; break;
case INDEX_op_shr_i32: case INDEX_op_shr_i32:
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr); t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_r(regs, &tb_ptr); t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, (uint32_t)t1 >> (t2 & 31)); tci_write_reg(regs, t0, (uint32_t)t1 >> (t2 & 31));
break; break;
case INDEX_op_sar_i32: case INDEX_op_sar_i32:
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr); t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_r(regs, &tb_ptr); t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, (int32_t)t1 >> (t2 & 31)); tci_write_reg(regs, t0, (int32_t)t1 >> (t2 & 31));
break; break;
#if TCG_TARGET_HAS_rot_i32 #if TCG_TARGET_HAS_rot_i32
case INDEX_op_rotl_i32: case INDEX_op_rotl_i32:
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr); t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_r(regs, &tb_ptr); t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, rol32(t1, t2 & 31)); tci_write_reg(regs, t0, rol32(t1, t2 & 31));
break; break;
case INDEX_op_rotr_i32: case INDEX_op_rotr_i32:
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr); t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_r(regs, &tb_ptr); t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, ror32(t1, t2 & 31)); tci_write_reg(regs, t0, ror32(t1, t2 & 31));
break; break;
#endif #endif
#if TCG_TARGET_HAS_deposit_i32 #if TCG_TARGET_HAS_deposit_i32
case INDEX_op_deposit_i32: case INDEX_op_deposit_i32:
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr); t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_r(regs, &tb_ptr); t2 = tci_read_rval(regs, &tb_ptr);
tmp16 = *tb_ptr++; tmp16 = *tb_ptr++;
tmp8 = *tb_ptr++; tmp8 = *tb_ptr++;
tmp32 = (((1 << tmp8) - 1) << tmp16); tmp32 = (((1 << tmp8) - 1) << tmp16);
@ -563,8 +563,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
break; break;
#endif #endif
case INDEX_op_brcond_i32: case INDEX_op_brcond_i32:
t0 = tci_read_r(regs, &tb_ptr); t0 = tci_read_rval(regs, &tb_ptr);
t1 = tci_read_r(regs, &tb_ptr); t1 = tci_read_rval(regs, &tb_ptr);
condition = *tb_ptr++; condition = *tb_ptr++;
label = tci_read_label(&tb_ptr); label = tci_read_label(&tb_ptr);
if (tci_compare32(t0, t1, condition)) { if (tci_compare32(t0, t1, condition)) {
@ -602,64 +602,64 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
case INDEX_op_mulu2_i32: case INDEX_op_mulu2_i32:
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = *tb_ptr++; t1 = *tb_ptr++;
t2 = tci_read_r(regs, &tb_ptr); t2 = tci_read_rval(regs, &tb_ptr);
tmp64 = (uint32_t)tci_read_r(regs, &tb_ptr); tmp64 = (uint32_t)tci_read_rval(regs, &tb_ptr);
tci_write_reg64(regs, t1, t0, (uint32_t)t2 * tmp64); tci_write_reg64(regs, t1, t0, (uint32_t)t2 * tmp64);
break; break;
#endif /* TCG_TARGET_REG_BITS == 32 */ #endif /* TCG_TARGET_REG_BITS == 32 */
#if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64
CASE_32_64(ext8s) CASE_32_64(ext8s)
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr); t1 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, (int8_t)t1); tci_write_reg(regs, t0, (int8_t)t1);
break; break;
#endif #endif
#if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64
CASE_32_64(ext16s) CASE_32_64(ext16s)
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr); t1 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, (int16_t)t1); tci_write_reg(regs, t0, (int16_t)t1);
break; break;
#endif #endif
#if TCG_TARGET_HAS_ext8u_i32 || TCG_TARGET_HAS_ext8u_i64 #if TCG_TARGET_HAS_ext8u_i32 || TCG_TARGET_HAS_ext8u_i64
CASE_32_64(ext8u) CASE_32_64(ext8u)
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr); t1 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, (uint8_t)t1); tci_write_reg(regs, t0, (uint8_t)t1);
break; break;
#endif #endif
#if TCG_TARGET_HAS_ext16u_i32 || TCG_TARGET_HAS_ext16u_i64 #if TCG_TARGET_HAS_ext16u_i32 || TCG_TARGET_HAS_ext16u_i64
CASE_32_64(ext16u) CASE_32_64(ext16u)
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr); t1 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, (uint16_t)t1); tci_write_reg(regs, t0, (uint16_t)t1);
break; break;
#endif #endif
#if TCG_TARGET_HAS_bswap16_i32 || TCG_TARGET_HAS_bswap16_i64 #if TCG_TARGET_HAS_bswap16_i32 || TCG_TARGET_HAS_bswap16_i64
CASE_32_64(bswap16) CASE_32_64(bswap16)
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr); t1 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, bswap16(t1)); tci_write_reg(regs, t0, bswap16(t1));
break; break;
#endif #endif
#if TCG_TARGET_HAS_bswap32_i32 || TCG_TARGET_HAS_bswap32_i64 #if TCG_TARGET_HAS_bswap32_i32 || TCG_TARGET_HAS_bswap32_i64
CASE_32_64(bswap32) CASE_32_64(bswap32)
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr); t1 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, bswap32(t1)); tci_write_reg(regs, t0, bswap32(t1));
break; break;
#endif #endif
#if TCG_TARGET_HAS_not_i32 || TCG_TARGET_HAS_not_i64 #if TCG_TARGET_HAS_not_i32 || TCG_TARGET_HAS_not_i64
CASE_32_64(not) CASE_32_64(not)
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr); t1 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, ~t1); tci_write_reg(regs, t0, ~t1);
break; break;
#endif #endif
#if TCG_TARGET_HAS_neg_i32 || TCG_TARGET_HAS_neg_i64 #if TCG_TARGET_HAS_neg_i32 || TCG_TARGET_HAS_neg_i64
CASE_32_64(neg) CASE_32_64(neg)
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr); t1 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, -t1); tci_write_reg(regs, t0, -t1);
break; break;
#endif #endif
@ -674,19 +674,19 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
case INDEX_op_ld32s_i64: case INDEX_op_ld32s_i64:
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr); t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_s32(&tb_ptr); t2 = tci_read_s32(&tb_ptr);
tci_write_reg(regs, t0, *(int32_t *)(t1 + t2)); tci_write_reg(regs, t0, *(int32_t *)(t1 + t2));
break; break;
case INDEX_op_ld_i64: case INDEX_op_ld_i64:
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr); t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_s32(&tb_ptr); t2 = tci_read_s32(&tb_ptr);
tci_write_reg(regs, t0, *(uint64_t *)(t1 + t2)); tci_write_reg(regs, t0, *(uint64_t *)(t1 + t2));
break; break;
case INDEX_op_st_i64: case INDEX_op_st_i64:
t0 = tci_read_r(regs, &tb_ptr); t0 = tci_read_rval(regs, &tb_ptr);
t1 = tci_read_r(regs, &tb_ptr); t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_s32(&tb_ptr); t2 = tci_read_s32(&tb_ptr);
*(uint64_t *)(t1 + t2) = t0; *(uint64_t *)(t1 + t2) = t0;
break; break;
@ -695,26 +695,26 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
case INDEX_op_div_i64: case INDEX_op_div_i64:
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr); t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_r(regs, &tb_ptr); t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, (int64_t)t1 / (int64_t)t2); tci_write_reg(regs, t0, (int64_t)t1 / (int64_t)t2);
break; break;
case INDEX_op_divu_i64: case INDEX_op_divu_i64:
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr); t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_r(regs, &tb_ptr); t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, (uint64_t)t1 / (uint64_t)t2); tci_write_reg(regs, t0, (uint64_t)t1 / (uint64_t)t2);
break; break;
case INDEX_op_rem_i64: case INDEX_op_rem_i64:
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr); t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_r(regs, &tb_ptr); t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, (int64_t)t1 % (int64_t)t2); tci_write_reg(regs, t0, (int64_t)t1 % (int64_t)t2);
break; break;
case INDEX_op_remu_i64: case INDEX_op_remu_i64:
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr); t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_r(regs, &tb_ptr); t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, (uint64_t)t1 % (uint64_t)t2); tci_write_reg(regs, t0, (uint64_t)t1 % (uint64_t)t2);
break; break;
@ -722,41 +722,41 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
case INDEX_op_shl_i64: case INDEX_op_shl_i64:
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr); t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_r(regs, &tb_ptr); t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 << (t2 & 63)); tci_write_reg(regs, t0, t1 << (t2 & 63));
break; break;
case INDEX_op_shr_i64: case INDEX_op_shr_i64:
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr); t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_r(regs, &tb_ptr); t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, t1 >> (t2 & 63)); tci_write_reg(regs, t0, t1 >> (t2 & 63));
break; break;
case INDEX_op_sar_i64: case INDEX_op_sar_i64:
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr); t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_r(regs, &tb_ptr); t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, ((int64_t)t1 >> (t2 & 63))); tci_write_reg(regs, t0, ((int64_t)t1 >> (t2 & 63)));
break; break;
#if TCG_TARGET_HAS_rot_i64 #if TCG_TARGET_HAS_rot_i64
case INDEX_op_rotl_i64: case INDEX_op_rotl_i64:
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr); t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_r(regs, &tb_ptr); t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, rol64(t1, t2 & 63)); tci_write_reg(regs, t0, rol64(t1, t2 & 63));
break; break;
case INDEX_op_rotr_i64: case INDEX_op_rotr_i64:
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr); t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_r(regs, &tb_ptr); t2 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, ror64(t1, t2 & 63)); tci_write_reg(regs, t0, ror64(t1, t2 & 63));
break; break;
#endif #endif
#if TCG_TARGET_HAS_deposit_i64 #if TCG_TARGET_HAS_deposit_i64
case INDEX_op_deposit_i64: case INDEX_op_deposit_i64:
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr); t1 = tci_read_rval(regs, &tb_ptr);
t2 = tci_read_r(regs, &tb_ptr); t2 = tci_read_rval(regs, &tb_ptr);
tmp16 = *tb_ptr++; tmp16 = *tb_ptr++;
tmp8 = *tb_ptr++; tmp8 = *tb_ptr++;
tmp64 = (((1ULL << tmp8) - 1) << tmp16); tmp64 = (((1ULL << tmp8) - 1) << tmp16);
@ -764,8 +764,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
break; break;
#endif #endif
case INDEX_op_brcond_i64: case INDEX_op_brcond_i64:
t0 = tci_read_r(regs, &tb_ptr); t0 = tci_read_rval(regs, &tb_ptr);
t1 = tci_read_r(regs, &tb_ptr); t1 = tci_read_rval(regs, &tb_ptr);
condition = *tb_ptr++; condition = *tb_ptr++;
label = tci_read_label(&tb_ptr); label = tci_read_label(&tb_ptr);
if (tci_compare64(t0, t1, condition)) { if (tci_compare64(t0, t1, condition)) {
@ -777,19 +777,19 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
case INDEX_op_ext32s_i64: case INDEX_op_ext32s_i64:
case INDEX_op_ext_i32_i64: case INDEX_op_ext_i32_i64:
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr); t1 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, (int32_t)t1); tci_write_reg(regs, t0, (int32_t)t1);
break; break;
case INDEX_op_ext32u_i64: case INDEX_op_ext32u_i64:
case INDEX_op_extu_i32_i64: case INDEX_op_extu_i32_i64:
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr); t1 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, (uint32_t)t1); tci_write_reg(regs, t0, (uint32_t)t1);
break; break;
#if TCG_TARGET_HAS_bswap64_i64 #if TCG_TARGET_HAS_bswap64_i64
case INDEX_op_bswap64_i64: case INDEX_op_bswap64_i64:
t0 = *tb_ptr++; t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr); t1 = tci_read_rval(regs, &tb_ptr);
tci_write_reg(regs, t0, bswap64(t1)); tci_write_reg(regs, t0, bswap64(t1));
break; break;
#endif #endif
@ -896,7 +896,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
} }
break; break;
case INDEX_op_qemu_st_i32: case INDEX_op_qemu_st_i32:
t0 = tci_read_r(regs, &tb_ptr); t0 = tci_read_rval(regs, &tb_ptr);
taddr = tci_read_ulong(regs, &tb_ptr); taddr = tci_read_ulong(regs, &tb_ptr);
oi = tci_read_i(&tb_ptr); oi = tci_read_i(&tb_ptr);
switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) { switch (get_memop(oi) & (MO_BSWAP | MO_SIZE)) {