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tcg: Rename cpu_env to tcg_env
Allow the name 'cpu_env' to be used for something else. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
a953b5fa15
commit
ad75a51e84
91 changed files with 3818 additions and 3819 deletions
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@ -86,7 +86,7 @@ tcg_funcs_generated.c.inc
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const int RdN = insn->regno[0];
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TCGv RsV = hex_gpr[insn->regno[1]];
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TCGv RtV = hex_gpr[insn->regno[2]];
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gen_helper_A2_add(RdV, cpu_env, RsV, RtV);
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gen_helper_A2_add(RdV, tcg_env, RsV, RtV);
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gen_log_reg_write(ctx, RdN, RdV);
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}
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@ -143,7 +143,7 @@ istruction.
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const intptr_t VdV_off =
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ctx_future_vreg_off(ctx, VdN, 1, true);
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TCGv_ptr VdV = tcg_temp_new_ptr();
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tcg_gen_addi_ptr(VdV, cpu_env, VdV_off);
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tcg_gen_addi_ptr(VdV, tcg_env, VdV_off);
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const int VuN = insn->regno[1];
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const intptr_t VuV_off =
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vreg_src_off(ctx, VuN);
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@ -152,9 +152,9 @@ istruction.
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const intptr_t VvV_off =
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vreg_src_off(ctx, VvN);
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TCGv_ptr VvV = tcg_temp_new_ptr();
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tcg_gen_addi_ptr(VuV, cpu_env, VuV_off);
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tcg_gen_addi_ptr(VvV, cpu_env, VvV_off);
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gen_helper_V6_vaddw(cpu_env, VdV, VuV, VvV);
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tcg_gen_addi_ptr(VuV, tcg_env, VuV_off);
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tcg_gen_addi_ptr(VvV, tcg_env, VvV_off);
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gen_helper_V6_vaddw(tcg_env, VdV, VuV, VvV);
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}
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Notice that we also generate a variable named <operand>_off for each operand of
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@ -591,8 +591,8 @@
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*/
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#define fGEN_TCG_A5_ACS(SHORTCODE) \
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do { \
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gen_helper_vacsh_pred(PeV, cpu_env, RxxV, RssV, RttV); \
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gen_helper_vacsh_val(RxxV, cpu_env, RxxV, RssV, RttV, \
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gen_helper_vacsh_pred(PeV, tcg_env, RxxV, RssV, RttV); \
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gen_helper_vacsh_val(RxxV, tcg_env, RxxV, RssV, RttV, \
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tcg_constant_tl(ctx->need_commit)); \
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} while (0)
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@ -614,7 +614,7 @@
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#define fGEN_TCG_F2_sfrecipa(SHORTCODE) \
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do { \
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TCGv_i64 tmp = tcg_temp_new_i64(); \
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gen_helper_sfrecipa(tmp, cpu_env, RsV, RtV); \
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gen_helper_sfrecipa(tmp, tcg_env, RsV, RtV); \
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tcg_gen_extrh_i64_i32(RdV, tmp); \
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tcg_gen_extrl_i64_i32(PeV, tmp); \
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} while (0)
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@ -629,7 +629,7 @@
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#define fGEN_TCG_F2_sfinvsqrta(SHORTCODE) \
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do { \
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TCGv_i64 tmp = tcg_temp_new_i64(); \
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gen_helper_sfinvsqrta(tmp, cpu_env, RsV); \
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gen_helper_sfinvsqrta(tmp, tcg_env, RsV); \
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tcg_gen_extrh_i64_i32(RdV, tmp); \
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tcg_gen_extrl_i64_i32(PeV, tmp); \
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} while (0)
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@ -1205,122 +1205,122 @@
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/* Floating point */
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#define fGEN_TCG_F2_conv_sf2df(SHORTCODE) \
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gen_helper_conv_sf2df(RddV, cpu_env, RsV)
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gen_helper_conv_sf2df(RddV, tcg_env, RsV)
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#define fGEN_TCG_F2_conv_df2sf(SHORTCODE) \
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gen_helper_conv_df2sf(RdV, cpu_env, RssV)
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gen_helper_conv_df2sf(RdV, tcg_env, RssV)
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#define fGEN_TCG_F2_conv_uw2sf(SHORTCODE) \
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gen_helper_conv_uw2sf(RdV, cpu_env, RsV)
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gen_helper_conv_uw2sf(RdV, tcg_env, RsV)
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#define fGEN_TCG_F2_conv_uw2df(SHORTCODE) \
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gen_helper_conv_uw2df(RddV, cpu_env, RsV)
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gen_helper_conv_uw2df(RddV, tcg_env, RsV)
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#define fGEN_TCG_F2_conv_w2sf(SHORTCODE) \
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gen_helper_conv_w2sf(RdV, cpu_env, RsV)
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gen_helper_conv_w2sf(RdV, tcg_env, RsV)
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#define fGEN_TCG_F2_conv_w2df(SHORTCODE) \
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gen_helper_conv_w2df(RddV, cpu_env, RsV)
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gen_helper_conv_w2df(RddV, tcg_env, RsV)
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#define fGEN_TCG_F2_conv_ud2sf(SHORTCODE) \
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gen_helper_conv_ud2sf(RdV, cpu_env, RssV)
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gen_helper_conv_ud2sf(RdV, tcg_env, RssV)
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#define fGEN_TCG_F2_conv_ud2df(SHORTCODE) \
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gen_helper_conv_ud2df(RddV, cpu_env, RssV)
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gen_helper_conv_ud2df(RddV, tcg_env, RssV)
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#define fGEN_TCG_F2_conv_d2sf(SHORTCODE) \
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gen_helper_conv_d2sf(RdV, cpu_env, RssV)
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gen_helper_conv_d2sf(RdV, tcg_env, RssV)
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#define fGEN_TCG_F2_conv_d2df(SHORTCODE) \
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gen_helper_conv_d2df(RddV, cpu_env, RssV)
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gen_helper_conv_d2df(RddV, tcg_env, RssV)
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#define fGEN_TCG_F2_conv_sf2uw(SHORTCODE) \
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gen_helper_conv_sf2uw(RdV, cpu_env, RsV)
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gen_helper_conv_sf2uw(RdV, tcg_env, RsV)
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#define fGEN_TCG_F2_conv_sf2w(SHORTCODE) \
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gen_helper_conv_sf2w(RdV, cpu_env, RsV)
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gen_helper_conv_sf2w(RdV, tcg_env, RsV)
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#define fGEN_TCG_F2_conv_sf2ud(SHORTCODE) \
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gen_helper_conv_sf2ud(RddV, cpu_env, RsV)
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gen_helper_conv_sf2ud(RddV, tcg_env, RsV)
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#define fGEN_TCG_F2_conv_sf2d(SHORTCODE) \
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gen_helper_conv_sf2d(RddV, cpu_env, RsV)
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gen_helper_conv_sf2d(RddV, tcg_env, RsV)
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#define fGEN_TCG_F2_conv_df2uw(SHORTCODE) \
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gen_helper_conv_df2uw(RdV, cpu_env, RssV)
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gen_helper_conv_df2uw(RdV, tcg_env, RssV)
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#define fGEN_TCG_F2_conv_df2w(SHORTCODE) \
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gen_helper_conv_df2w(RdV, cpu_env, RssV)
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gen_helper_conv_df2w(RdV, tcg_env, RssV)
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#define fGEN_TCG_F2_conv_df2ud(SHORTCODE) \
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gen_helper_conv_df2ud(RddV, cpu_env, RssV)
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gen_helper_conv_df2ud(RddV, tcg_env, RssV)
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#define fGEN_TCG_F2_conv_df2d(SHORTCODE) \
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gen_helper_conv_df2d(RddV, cpu_env, RssV)
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gen_helper_conv_df2d(RddV, tcg_env, RssV)
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#define fGEN_TCG_F2_conv_sf2uw_chop(SHORTCODE) \
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gen_helper_conv_sf2uw_chop(RdV, cpu_env, RsV)
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gen_helper_conv_sf2uw_chop(RdV, tcg_env, RsV)
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#define fGEN_TCG_F2_conv_sf2w_chop(SHORTCODE) \
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gen_helper_conv_sf2w_chop(RdV, cpu_env, RsV)
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gen_helper_conv_sf2w_chop(RdV, tcg_env, RsV)
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#define fGEN_TCG_F2_conv_sf2ud_chop(SHORTCODE) \
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gen_helper_conv_sf2ud_chop(RddV, cpu_env, RsV)
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gen_helper_conv_sf2ud_chop(RddV, tcg_env, RsV)
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#define fGEN_TCG_F2_conv_sf2d_chop(SHORTCODE) \
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gen_helper_conv_sf2d_chop(RddV, cpu_env, RsV)
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gen_helper_conv_sf2d_chop(RddV, tcg_env, RsV)
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#define fGEN_TCG_F2_conv_df2uw_chop(SHORTCODE) \
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gen_helper_conv_df2uw_chop(RdV, cpu_env, RssV)
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gen_helper_conv_df2uw_chop(RdV, tcg_env, RssV)
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#define fGEN_TCG_F2_conv_df2w_chop(SHORTCODE) \
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gen_helper_conv_df2w_chop(RdV, cpu_env, RssV)
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gen_helper_conv_df2w_chop(RdV, tcg_env, RssV)
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#define fGEN_TCG_F2_conv_df2ud_chop(SHORTCODE) \
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gen_helper_conv_df2ud_chop(RddV, cpu_env, RssV)
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gen_helper_conv_df2ud_chop(RddV, tcg_env, RssV)
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#define fGEN_TCG_F2_conv_df2d_chop(SHORTCODE) \
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gen_helper_conv_df2d_chop(RddV, cpu_env, RssV)
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gen_helper_conv_df2d_chop(RddV, tcg_env, RssV)
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#define fGEN_TCG_F2_sfadd(SHORTCODE) \
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gen_helper_sfadd(RdV, cpu_env, RsV, RtV)
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gen_helper_sfadd(RdV, tcg_env, RsV, RtV)
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#define fGEN_TCG_F2_sfsub(SHORTCODE) \
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gen_helper_sfsub(RdV, cpu_env, RsV, RtV)
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gen_helper_sfsub(RdV, tcg_env, RsV, RtV)
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#define fGEN_TCG_F2_sfcmpeq(SHORTCODE) \
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gen_helper_sfcmpeq(PdV, cpu_env, RsV, RtV)
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gen_helper_sfcmpeq(PdV, tcg_env, RsV, RtV)
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#define fGEN_TCG_F2_sfcmpgt(SHORTCODE) \
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gen_helper_sfcmpgt(PdV, cpu_env, RsV, RtV)
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gen_helper_sfcmpgt(PdV, tcg_env, RsV, RtV)
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#define fGEN_TCG_F2_sfcmpge(SHORTCODE) \
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gen_helper_sfcmpge(PdV, cpu_env, RsV, RtV)
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gen_helper_sfcmpge(PdV, tcg_env, RsV, RtV)
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#define fGEN_TCG_F2_sfcmpuo(SHORTCODE) \
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gen_helper_sfcmpuo(PdV, cpu_env, RsV, RtV)
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gen_helper_sfcmpuo(PdV, tcg_env, RsV, RtV)
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#define fGEN_TCG_F2_sfmax(SHORTCODE) \
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gen_helper_sfmax(RdV, cpu_env, RsV, RtV)
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gen_helper_sfmax(RdV, tcg_env, RsV, RtV)
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#define fGEN_TCG_F2_sfmin(SHORTCODE) \
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gen_helper_sfmin(RdV, cpu_env, RsV, RtV)
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gen_helper_sfmin(RdV, tcg_env, RsV, RtV)
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#define fGEN_TCG_F2_sfclass(SHORTCODE) \
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do { \
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TCGv imm = tcg_constant_tl(uiV); \
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gen_helper_sfclass(PdV, cpu_env, RsV, imm); \
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gen_helper_sfclass(PdV, tcg_env, RsV, imm); \
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} while (0)
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#define fGEN_TCG_F2_sffixupn(SHORTCODE) \
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gen_helper_sffixupn(RdV, cpu_env, RsV, RtV)
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gen_helper_sffixupn(RdV, tcg_env, RsV, RtV)
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#define fGEN_TCG_F2_sffixupd(SHORTCODE) \
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gen_helper_sffixupd(RdV, cpu_env, RsV, RtV)
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gen_helper_sffixupd(RdV, tcg_env, RsV, RtV)
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#define fGEN_TCG_F2_sffixupr(SHORTCODE) \
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gen_helper_sffixupr(RdV, cpu_env, RsV)
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gen_helper_sffixupr(RdV, tcg_env, RsV)
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#define fGEN_TCG_F2_dfadd(SHORTCODE) \
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gen_helper_dfadd(RddV, cpu_env, RssV, RttV)
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gen_helper_dfadd(RddV, tcg_env, RssV, RttV)
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#define fGEN_TCG_F2_dfsub(SHORTCODE) \
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gen_helper_dfsub(RddV, cpu_env, RssV, RttV)
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gen_helper_dfsub(RddV, tcg_env, RssV, RttV)
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#define fGEN_TCG_F2_dfmax(SHORTCODE) \
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gen_helper_dfmax(RddV, cpu_env, RssV, RttV)
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gen_helper_dfmax(RddV, tcg_env, RssV, RttV)
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#define fGEN_TCG_F2_dfmin(SHORTCODE) \
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gen_helper_dfmin(RddV, cpu_env, RssV, RttV)
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gen_helper_dfmin(RddV, tcg_env, RssV, RttV)
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#define fGEN_TCG_F2_dfcmpeq(SHORTCODE) \
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gen_helper_dfcmpeq(PdV, cpu_env, RssV, RttV)
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gen_helper_dfcmpeq(PdV, tcg_env, RssV, RttV)
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#define fGEN_TCG_F2_dfcmpgt(SHORTCODE) \
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gen_helper_dfcmpgt(PdV, cpu_env, RssV, RttV)
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gen_helper_dfcmpgt(PdV, tcg_env, RssV, RttV)
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#define fGEN_TCG_F2_dfcmpge(SHORTCODE) \
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gen_helper_dfcmpge(PdV, cpu_env, RssV, RttV)
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gen_helper_dfcmpge(PdV, tcg_env, RssV, RttV)
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#define fGEN_TCG_F2_dfcmpuo(SHORTCODE) \
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gen_helper_dfcmpuo(PdV, cpu_env, RssV, RttV)
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gen_helper_dfcmpuo(PdV, tcg_env, RssV, RttV)
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#define fGEN_TCG_F2_dfclass(SHORTCODE) \
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do { \
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TCGv imm = tcg_constant_tl(uiV); \
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gen_helper_dfclass(PdV, cpu_env, RssV, imm); \
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gen_helper_dfclass(PdV, tcg_env, RssV, imm); \
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} while (0)
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#define fGEN_TCG_F2_sfmpy(SHORTCODE) \
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gen_helper_sfmpy(RdV, cpu_env, RsV, RtV)
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gen_helper_sfmpy(RdV, tcg_env, RsV, RtV)
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#define fGEN_TCG_F2_sffma(SHORTCODE) \
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gen_helper_sffma(RxV, cpu_env, RxV, RsV, RtV)
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gen_helper_sffma(RxV, tcg_env, RxV, RsV, RtV)
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#define fGEN_TCG_F2_sffma_sc(SHORTCODE) \
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gen_helper_sffma_sc(RxV, cpu_env, RxV, RsV, RtV, PuV)
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gen_helper_sffma_sc(RxV, tcg_env, RxV, RsV, RtV, PuV)
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#define fGEN_TCG_F2_sffms(SHORTCODE) \
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gen_helper_sffms(RxV, cpu_env, RxV, RsV, RtV)
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gen_helper_sffms(RxV, tcg_env, RxV, RsV, RtV)
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#define fGEN_TCG_F2_sffma_lib(SHORTCODE) \
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gen_helper_sffma_lib(RxV, cpu_env, RxV, RsV, RtV)
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gen_helper_sffma_lib(RxV, tcg_env, RxV, RsV, RtV)
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#define fGEN_TCG_F2_sffms_lib(SHORTCODE) \
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gen_helper_sffms_lib(RxV, cpu_env, RxV, RsV, RtV)
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gen_helper_sffms_lib(RxV, tcg_env, RxV, RsV, RtV)
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#define fGEN_TCG_F2_dfmpyfix(SHORTCODE) \
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gen_helper_dfmpyfix(RddV, cpu_env, RssV, RttV)
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gen_helper_dfmpyfix(RddV, tcg_env, RssV, RttV)
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#define fGEN_TCG_F2_dfmpyhh(SHORTCODE) \
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gen_helper_dfmpyhh(RxxV, cpu_env, RxxV, RssV, RttV)
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gen_helper_dfmpyhh(RxxV, tcg_env, RxxV, RssV, RttV)
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/* Nothing to do for these in qemu, need to suppress compiler warnings */
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#define fGEN_TCG_Y4_l2fetch(SHORTCODE) \
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@ -1367,6 +1367,6 @@
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uiV = uiV; \
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tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->pkt->pc); \
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TCGv excp = tcg_constant_tl(HEX_EXCP_TRAP0); \
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gen_helper_raise_exception(cpu_env, excp); \
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gen_helper_raise_exception(tcg_env, excp); \
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} while (0)
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#endif
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@ -120,7 +120,7 @@ def genptr_decl(f, tag, regtype, regid, regno):
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if not hex_common.skip_qemu_helper(tag):
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f.write(f" TCGv_ptr {regtype}{regid}V = " "tcg_temp_new_ptr();\n")
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f.write(
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f" tcg_gen_addi_ptr({regtype}{regid}V, cpu_env, "
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f" tcg_gen_addi_ptr({regtype}{regid}V, tcg_env, "
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f"{regtype}{regid}V_off);\n"
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)
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elif regid in {"uu", "vv", "xx"}:
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@ -130,7 +130,7 @@ def genptr_decl(f, tag, regtype, regid, regno):
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if not hex_common.skip_qemu_helper(tag):
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f.write(f" TCGv_ptr {regtype}{regid}V = " "tcg_temp_new_ptr();\n")
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f.write(
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f" tcg_gen_addi_ptr({regtype}{regid}V, cpu_env, "
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f" tcg_gen_addi_ptr({regtype}{regid}V, tcg_env, "
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f"{regtype}{regid}V_off);\n"
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)
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elif regid in {"s", "u", "v", "w"}:
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@ -155,7 +155,7 @@ def genptr_decl(f, tag, regtype, regid, regno):
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if not hex_common.skip_qemu_helper(tag):
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f.write(f" TCGv_ptr {regtype}{regid}V = " "tcg_temp_new_ptr();\n")
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f.write(
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f" tcg_gen_addi_ptr({regtype}{regid}V, cpu_env, "
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f" tcg_gen_addi_ptr({regtype}{regid}V, tcg_env, "
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f"{regtype}{regid}V_off);\n"
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)
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else:
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@ -168,7 +168,7 @@ def genptr_decl(f, tag, regtype, regid, regno):
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if not hex_common.skip_qemu_helper(tag):
|
||||
f.write(f" TCGv_ptr {regtype}{regid}V = " "tcg_temp_new_ptr();\n")
|
||||
f.write(
|
||||
f" tcg_gen_addi_ptr({regtype}{regid}V, cpu_env, "
|
||||
f" tcg_gen_addi_ptr({regtype}{regid}V, tcg_env, "
|
||||
f"{regtype}{regid}V_off);\n"
|
||||
)
|
||||
elif regid in {"s", "t", "u", "v"}:
|
||||
|
|
@ -303,7 +303,7 @@ def genptr_src_read(f, tag, regtype, regid):
|
|||
elif regid in {"s", "u", "v", "w"}:
|
||||
if not hex_common.skip_qemu_helper(tag):
|
||||
f.write(
|
||||
f" tcg_gen_addi_ptr({regtype}{regid}V, cpu_env, "
|
||||
f" tcg_gen_addi_ptr({regtype}{regid}V, tcg_env, "
|
||||
f"{regtype}{regid}V_off);\n"
|
||||
)
|
||||
elif regid in {"x", "y"}:
|
||||
|
|
@ -316,7 +316,7 @@ def genptr_src_read(f, tag, regtype, regid):
|
|||
if regid in {"s", "t", "u", "v"}:
|
||||
if not hex_common.skip_qemu_helper(tag):
|
||||
f.write(
|
||||
f" tcg_gen_addi_ptr({regtype}{regid}V, cpu_env, "
|
||||
f" tcg_gen_addi_ptr({regtype}{regid}V, tcg_env, "
|
||||
f"{regtype}{regid}V_off);\n"
|
||||
)
|
||||
elif regid in {"x"}:
|
||||
|
|
@ -490,7 +490,7 @@ def genptr_dst_write_opn(f, regtype, regid, tag):
|
|||
## if hex_common.skip_qemu_helper(tag) is True
|
||||
## <GEN> is fGEN_TCG_A2_add({ RdV=RsV+RtV;});
|
||||
## if hex_common.skip_qemu_helper(tag) is False
|
||||
## <GEN> is gen_helper_A2_add(RdV, cpu_env, RsV, RtV);
|
||||
## <GEN> is gen_helper_A2_add(RdV, tcg_env, RsV, RtV);
|
||||
##
|
||||
def gen_tcg_func(f, tag, regs, imms):
|
||||
f.write(f"static void generate_{tag}(DisasContext *ctx)\n")
|
||||
|
|
@ -572,7 +572,7 @@ def gen_tcg_func(f, tag, regs, imms):
|
|||
i += 1
|
||||
if i > 0:
|
||||
f.write(", ")
|
||||
f.write("cpu_env")
|
||||
f.write("tcg_env")
|
||||
i = 1
|
||||
## For conditional instructions, we pass in the destination register
|
||||
if "A_CONDEXEC" in hex_common.attribdict[tag]:
|
||||
|
|
|
|||
|
|
@ -43,7 +43,7 @@ static inline void assert_vhist_tmp(DisasContext *ctx)
|
|||
#define fGEN_TCG_V6_vhist(SHORTCODE) \
|
||||
if (!ctx->pre_commit) { \
|
||||
assert_vhist_tmp(ctx); \
|
||||
gen_helper_vhist(cpu_env); \
|
||||
gen_helper_vhist(tcg_env); \
|
||||
}
|
||||
#define fGEN_TCG_V6_vhistq(SHORTCODE) \
|
||||
do { \
|
||||
|
|
@ -53,13 +53,13 @@ static inline void assert_vhist_tmp(DisasContext *ctx)
|
|||
sizeof(MMVector), sizeof(MMVector)); \
|
||||
} else { \
|
||||
assert_vhist_tmp(ctx); \
|
||||
gen_helper_vhistq(cpu_env); \
|
||||
gen_helper_vhistq(tcg_env); \
|
||||
} \
|
||||
} while (0)
|
||||
#define fGEN_TCG_V6_vwhist256(SHORTCODE) \
|
||||
if (!ctx->pre_commit) { \
|
||||
assert_vhist_tmp(ctx); \
|
||||
gen_helper_vwhist256(cpu_env); \
|
||||
gen_helper_vwhist256(tcg_env); \
|
||||
}
|
||||
#define fGEN_TCG_V6_vwhist256q(SHORTCODE) \
|
||||
do { \
|
||||
|
|
@ -69,13 +69,13 @@ static inline void assert_vhist_tmp(DisasContext *ctx)
|
|||
sizeof(MMVector), sizeof(MMVector)); \
|
||||
} else { \
|
||||
assert_vhist_tmp(ctx); \
|
||||
gen_helper_vwhist256q(cpu_env); \
|
||||
gen_helper_vwhist256q(tcg_env); \
|
||||
} \
|
||||
} while (0)
|
||||
#define fGEN_TCG_V6_vwhist256_sat(SHORTCODE) \
|
||||
if (!ctx->pre_commit) { \
|
||||
assert_vhist_tmp(ctx); \
|
||||
gen_helper_vwhist256_sat(cpu_env); \
|
||||
gen_helper_vwhist256_sat(tcg_env); \
|
||||
}
|
||||
#define fGEN_TCG_V6_vwhist256q_sat(SHORTCODE) \
|
||||
do { \
|
||||
|
|
@ -85,13 +85,13 @@ static inline void assert_vhist_tmp(DisasContext *ctx)
|
|||
sizeof(MMVector), sizeof(MMVector)); \
|
||||
} else { \
|
||||
assert_vhist_tmp(ctx); \
|
||||
gen_helper_vwhist256q_sat(cpu_env); \
|
||||
gen_helper_vwhist256q_sat(tcg_env); \
|
||||
} \
|
||||
} while (0)
|
||||
#define fGEN_TCG_V6_vwhist128(SHORTCODE) \
|
||||
if (!ctx->pre_commit) { \
|
||||
assert_vhist_tmp(ctx); \
|
||||
gen_helper_vwhist128(cpu_env); \
|
||||
gen_helper_vwhist128(tcg_env); \
|
||||
}
|
||||
#define fGEN_TCG_V6_vwhist128q(SHORTCODE) \
|
||||
do { \
|
||||
|
|
@ -101,14 +101,14 @@ static inline void assert_vhist_tmp(DisasContext *ctx)
|
|||
sizeof(MMVector), sizeof(MMVector)); \
|
||||
} else { \
|
||||
assert_vhist_tmp(ctx); \
|
||||
gen_helper_vwhist128q(cpu_env); \
|
||||
gen_helper_vwhist128q(tcg_env); \
|
||||
} \
|
||||
} while (0)
|
||||
#define fGEN_TCG_V6_vwhist128m(SHORTCODE) \
|
||||
if (!ctx->pre_commit) { \
|
||||
TCGv tcgv_uiV = tcg_constant_tl(uiV); \
|
||||
assert_vhist_tmp(ctx); \
|
||||
gen_helper_vwhist128m(cpu_env, tcgv_uiV); \
|
||||
gen_helper_vwhist128m(tcg_env, tcgv_uiV); \
|
||||
}
|
||||
#define fGEN_TCG_V6_vwhist128qm(SHORTCODE) \
|
||||
do { \
|
||||
|
|
@ -119,7 +119,7 @@ static inline void assert_vhist_tmp(DisasContext *ctx)
|
|||
} else { \
|
||||
TCGv tcgv_uiV = tcg_constant_tl(uiV); \
|
||||
assert_vhist_tmp(ctx); \
|
||||
gen_helper_vwhist128qm(cpu_env, tcgv_uiV); \
|
||||
gen_helper_vwhist128qm(tcg_env, tcgv_uiV); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
|
|
|
|||
|
|
@ -414,50 +414,50 @@ void gen_store32(TCGv vaddr, TCGv src, int width, uint32_t slot)
|
|||
tcg_gen_mov_tl(hex_store_val32[slot], src);
|
||||
}
|
||||
|
||||
void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot)
|
||||
void gen_store1(TCGv_env tcg_env, TCGv vaddr, TCGv src, uint32_t slot)
|
||||
{
|
||||
gen_store32(vaddr, src, 1, slot);
|
||||
}
|
||||
|
||||
void gen_store1i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot)
|
||||
void gen_store1i(TCGv_env tcg_env, TCGv vaddr, int32_t src, uint32_t slot)
|
||||
{
|
||||
TCGv tmp = tcg_constant_tl(src);
|
||||
gen_store1(cpu_env, vaddr, tmp, slot);
|
||||
gen_store1(tcg_env, vaddr, tmp, slot);
|
||||
}
|
||||
|
||||
void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot)
|
||||
void gen_store2(TCGv_env tcg_env, TCGv vaddr, TCGv src, uint32_t slot)
|
||||
{
|
||||
gen_store32(vaddr, src, 2, slot);
|
||||
}
|
||||
|
||||
void gen_store2i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot)
|
||||
void gen_store2i(TCGv_env tcg_env, TCGv vaddr, int32_t src, uint32_t slot)
|
||||
{
|
||||
TCGv tmp = tcg_constant_tl(src);
|
||||
gen_store2(cpu_env, vaddr, tmp, slot);
|
||||
gen_store2(tcg_env, vaddr, tmp, slot);
|
||||
}
|
||||
|
||||
void gen_store4(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot)
|
||||
void gen_store4(TCGv_env tcg_env, TCGv vaddr, TCGv src, uint32_t slot)
|
||||
{
|
||||
gen_store32(vaddr, src, 4, slot);
|
||||
}
|
||||
|
||||
void gen_store4i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot)
|
||||
void gen_store4i(TCGv_env tcg_env, TCGv vaddr, int32_t src, uint32_t slot)
|
||||
{
|
||||
TCGv tmp = tcg_constant_tl(src);
|
||||
gen_store4(cpu_env, vaddr, tmp, slot);
|
||||
gen_store4(tcg_env, vaddr, tmp, slot);
|
||||
}
|
||||
|
||||
void gen_store8(TCGv_env cpu_env, TCGv vaddr, TCGv_i64 src, uint32_t slot)
|
||||
void gen_store8(TCGv_env tcg_env, TCGv vaddr, TCGv_i64 src, uint32_t slot)
|
||||
{
|
||||
tcg_gen_mov_tl(hex_store_addr[slot], vaddr);
|
||||
tcg_gen_movi_tl(hex_store_width[slot], 8);
|
||||
tcg_gen_mov_i64(hex_store_val64[slot], src);
|
||||
}
|
||||
|
||||
void gen_store8i(TCGv_env cpu_env, TCGv vaddr, int64_t src, uint32_t slot)
|
||||
void gen_store8i(TCGv_env tcg_env, TCGv vaddr, int64_t src, uint32_t slot)
|
||||
{
|
||||
TCGv_i64 tmp = tcg_constant_i64(src);
|
||||
gen_store8(cpu_env, vaddr, tmp, slot);
|
||||
gen_store8(tcg_env, vaddr, tmp, slot);
|
||||
}
|
||||
|
||||
TCGv gen_8bitsof(TCGv result, TCGv value)
|
||||
|
|
@ -783,7 +783,7 @@ static void gen_allocframe(DisasContext *ctx, TCGv r29, int framesize)
|
|||
TCGv_i64 frame;
|
||||
tcg_gen_addi_tl(r30, r29, -8);
|
||||
frame = gen_frame_scramble();
|
||||
gen_store8(cpu_env, r30, frame, ctx->insn->slot);
|
||||
gen_store8(tcg_env, r30, frame, ctx->insn->slot);
|
||||
gen_log_reg_write(ctx, HEX_REG_FP, r30);
|
||||
gen_framecheck(r30, framesize);
|
||||
tcg_gen_subi_tl(r29, r30, framesize);
|
||||
|
|
@ -1239,7 +1239,7 @@ static void gen_vreg_load(DisasContext *ctx, intptr_t dstoff, TCGv src,
|
|||
for (int i = 0; i < sizeof(MMVector) / 8; i++) {
|
||||
tcg_gen_qemu_ld_i64(tmp, src, ctx->mem_idx, MO_TEUQ);
|
||||
tcg_gen_addi_tl(src, src, 8);
|
||||
tcg_gen_st_i64(tmp, cpu_env, dstoff + i * 8);
|
||||
tcg_gen_st_i64(tmp, tcg_env, dstoff + i * 8);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1251,7 +1251,7 @@ static void gen_vreg_store(DisasContext *ctx, TCGv EA, intptr_t srcoff,
|
|||
|
||||
if (is_gather_store_insn(ctx)) {
|
||||
TCGv sl = tcg_constant_tl(slot);
|
||||
gen_helper_gather_store(cpu_env, EA, sl);
|
||||
gen_helper_gather_store(tcg_env, EA, sl);
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -1301,7 +1301,7 @@ static void vec_to_qvec(size_t size, intptr_t dstoff, intptr_t srcoff)
|
|||
TCGv_i64 ones = tcg_constant_i64(~0);
|
||||
|
||||
for (int i = 0; i < sizeof(MMVector) / 8; i++) {
|
||||
tcg_gen_ld_i64(tmp, cpu_env, srcoff + i * 8);
|
||||
tcg_gen_ld_i64(tmp, tcg_env, srcoff + i * 8);
|
||||
tcg_gen_movi_i64(mask, 0);
|
||||
|
||||
for (int j = 0; j < 8; j += size) {
|
||||
|
|
@ -1310,7 +1310,7 @@ static void vec_to_qvec(size_t size, intptr_t dstoff, intptr_t srcoff)
|
|||
tcg_gen_deposit_i64(mask, mask, bits, j, size);
|
||||
}
|
||||
|
||||
tcg_gen_st8_i64(mask, cpu_env, dstoff + i);
|
||||
tcg_gen_st8_i64(mask, tcg_env, dstoff + i);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1318,7 +1318,7 @@ void probe_noshuf_load(TCGv va, int s, int mi)
|
|||
{
|
||||
TCGv size = tcg_constant_tl(s);
|
||||
TCGv mem_idx = tcg_constant_tl(mi);
|
||||
gen_helper_probe_noshuf_load(cpu_env, va, size, mem_idx);
|
||||
gen_helper_probe_noshuf_load(tcg_env, va, size, mem_idx);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -1773,7 +1773,7 @@ void gen_store(Context *c, YYLTYPE *locp, HexValue *width, HexValue *ea,
|
|||
/* Lookup the effective address EA */
|
||||
find_variable(c, locp, ea, ea);
|
||||
src_m = rvalue_materialize(c, locp, &src_m);
|
||||
OUT(c, locp, "gen_store", &mem_width, "(cpu_env, ", ea, ", ", &src_m);
|
||||
OUT(c, locp, "gen_store", &mem_width, "(tcg_env, ", ea, ", ", &src_m);
|
||||
OUT(c, locp, ", insn->slot);\n");
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -147,7 +147,7 @@
|
|||
__builtin_choose_expr(TYPE_TCGV(X), \
|
||||
gen_store1, (void)0))
|
||||
#define MEM_STORE1(VA, DATA, SLOT) \
|
||||
MEM_STORE1_FUNC(DATA)(cpu_env, VA, DATA, SLOT)
|
||||
MEM_STORE1_FUNC(DATA)(tcg_env, VA, DATA, SLOT)
|
||||
|
||||
#define MEM_STORE2_FUNC(X) \
|
||||
__builtin_choose_expr(TYPE_INT(X), \
|
||||
|
|
@ -155,7 +155,7 @@
|
|||
__builtin_choose_expr(TYPE_TCGV(X), \
|
||||
gen_store2, (void)0))
|
||||
#define MEM_STORE2(VA, DATA, SLOT) \
|
||||
MEM_STORE2_FUNC(DATA)(cpu_env, VA, DATA, SLOT)
|
||||
MEM_STORE2_FUNC(DATA)(tcg_env, VA, DATA, SLOT)
|
||||
|
||||
#define MEM_STORE4_FUNC(X) \
|
||||
__builtin_choose_expr(TYPE_INT(X), \
|
||||
|
|
@ -163,7 +163,7 @@
|
|||
__builtin_choose_expr(TYPE_TCGV(X), \
|
||||
gen_store4, (void)0))
|
||||
#define MEM_STORE4(VA, DATA, SLOT) \
|
||||
MEM_STORE4_FUNC(DATA)(cpu_env, VA, DATA, SLOT)
|
||||
MEM_STORE4_FUNC(DATA)(tcg_env, VA, DATA, SLOT)
|
||||
|
||||
#define MEM_STORE8_FUNC(X) \
|
||||
__builtin_choose_expr(TYPE_INT(X), \
|
||||
|
|
@ -171,7 +171,7 @@
|
|||
__builtin_choose_expr(TYPE_TCGV_I64(X), \
|
||||
gen_store8, (void)0))
|
||||
#define MEM_STORE8(VA, DATA, SLOT) \
|
||||
MEM_STORE8_FUNC(DATA)(cpu_env, VA, DATA, SLOT)
|
||||
MEM_STORE8_FUNC(DATA)(tcg_env, VA, DATA, SLOT)
|
||||
#else
|
||||
#define MEM_LOAD1s(VA) ((int8_t)mem_load1(env, pkt_has_store_s1, slot, VA))
|
||||
#define MEM_LOAD1u(VA) ((uint8_t)mem_load1(env, pkt_has_store_s1, slot, VA))
|
||||
|
|
|
|||
|
|
@ -115,7 +115,7 @@ intptr_t ctx_tmp_vreg_off(DisasContext *ctx, int regnum,
|
|||
|
||||
static void gen_exception_raw(int excp)
|
||||
{
|
||||
gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
|
||||
gen_helper_raise_exception(tcg_env, tcg_constant_i32(excp));
|
||||
}
|
||||
|
||||
static void gen_exec_counters(DisasContext *ctx)
|
||||
|
|
@ -528,7 +528,7 @@ static void gen_start_packet(DisasContext *ctx)
|
|||
|
||||
if (HEX_DEBUG) {
|
||||
/* Handy place to set a breakpoint before the packet executes */
|
||||
gen_helper_debug_start_packet(cpu_env);
|
||||
gen_helper_debug_start_packet(tcg_env);
|
||||
}
|
||||
|
||||
/* Initialize the runtime state for packet semantics */
|
||||
|
|
@ -701,7 +701,7 @@ static void gen_check_store_width(DisasContext *ctx, int slot_num)
|
|||
if (HEX_DEBUG) {
|
||||
TCGv slot = tcg_constant_tl(slot_num);
|
||||
TCGv check = tcg_constant_tl(ctx->store_width[slot_num]);
|
||||
gen_helper_debug_check_store_width(cpu_env, slot, check);
|
||||
gen_helper_debug_check_store_width(tcg_env, slot, check);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -783,7 +783,7 @@ void process_store(DisasContext *ctx, int slot_num)
|
|||
* avoid branching based on the width at runtime.
|
||||
*/
|
||||
TCGv slot = tcg_constant_tl(slot_num);
|
||||
gen_helper_commit_store(cpu_env, slot);
|
||||
gen_helper_commit_store(tcg_env, slot);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -882,7 +882,7 @@ static void gen_commit_hvx(DisasContext *ctx)
|
|||
}
|
||||
|
||||
if (pkt_has_hvx_store(ctx->pkt)) {
|
||||
gen_helper_commit_hvx_stores(cpu_env);
|
||||
gen_helper_commit_hvx_stores(tcg_env);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -942,7 +942,7 @@ static void gen_commit_packet(DisasContext *ctx)
|
|||
} else if (has_hvx_store) {
|
||||
if (!has_store_s0 && !has_store_s1) {
|
||||
TCGv mem_idx = tcg_constant_tl(ctx->mem_idx);
|
||||
gen_helper_probe_hvx_stores(cpu_env, mem_idx);
|
||||
gen_helper_probe_hvx_stores(tcg_env, mem_idx);
|
||||
} else {
|
||||
int mask = 0;
|
||||
|
||||
|
|
@ -971,7 +971,7 @@ static void gen_commit_packet(DisasContext *ctx)
|
|||
}
|
||||
mask = FIELD_DP32(mask, PROBE_PKT_SCALAR_HVX_STORES, MMU_IDX,
|
||||
ctx->mem_idx);
|
||||
gen_helper_probe_pkt_scalar_hvx_stores(cpu_env,
|
||||
gen_helper_probe_pkt_scalar_hvx_stores(tcg_env,
|
||||
tcg_constant_tl(mask));
|
||||
}
|
||||
} else if (has_store_s0 && has_store_s1) {
|
||||
|
|
@ -987,7 +987,7 @@ static void gen_commit_packet(DisasContext *ctx)
|
|||
FIELD_DP32(args, PROBE_PKT_SCALAR_STORE_S0, IS_PREDICATED, 1);
|
||||
}
|
||||
TCGv args_tcgv = tcg_constant_tl(args);
|
||||
gen_helper_probe_pkt_scalar_store_s0(cpu_env, args_tcgv);
|
||||
gen_helper_probe_pkt_scalar_store_s0(tcg_env, args_tcgv);
|
||||
}
|
||||
|
||||
process_store_log(ctx);
|
||||
|
|
@ -1005,7 +1005,7 @@ static void gen_commit_packet(DisasContext *ctx)
|
|||
tcg_constant_tl(pkt->pkt_has_store_s1 && !pkt->pkt_has_dczeroa);
|
||||
|
||||
/* Handy place to set a breakpoint at the end of execution */
|
||||
gen_helper_debug_commit_end(cpu_env, tcg_constant_tl(ctx->pkt->pc),
|
||||
gen_helper_debug_commit_end(tcg_env, tcg_constant_tl(ctx->pkt->pc),
|
||||
ctx->pred_written, has_st0, has_st1);
|
||||
}
|
||||
|
||||
|
|
@ -1179,68 +1179,68 @@ void hexagon_translate_init(void)
|
|||
opcode_init();
|
||||
|
||||
for (i = 0; i < TOTAL_PER_THREAD_REGS; i++) {
|
||||
hex_gpr[i] = tcg_global_mem_new(cpu_env,
|
||||
hex_gpr[i] = tcg_global_mem_new(tcg_env,
|
||||
offsetof(CPUHexagonState, gpr[i]),
|
||||
hexagon_regnames[i]);
|
||||
|
||||
if (HEX_DEBUG) {
|
||||
snprintf(reg_written_names[i], NAME_LEN, "reg_written_%s",
|
||||
hexagon_regnames[i]);
|
||||
hex_reg_written[i] = tcg_global_mem_new(cpu_env,
|
||||
hex_reg_written[i] = tcg_global_mem_new(tcg_env,
|
||||
offsetof(CPUHexagonState, reg_written[i]),
|
||||
reg_written_names[i]);
|
||||
}
|
||||
}
|
||||
hex_new_value_usr = tcg_global_mem_new(cpu_env,
|
||||
hex_new_value_usr = tcg_global_mem_new(tcg_env,
|
||||
offsetof(CPUHexagonState, new_value_usr), "new_value_usr");
|
||||
|
||||
for (i = 0; i < NUM_PREGS; i++) {
|
||||
hex_pred[i] = tcg_global_mem_new(cpu_env,
|
||||
hex_pred[i] = tcg_global_mem_new(tcg_env,
|
||||
offsetof(CPUHexagonState, pred[i]),
|
||||
hexagon_prednames[i]);
|
||||
}
|
||||
hex_slot_cancelled = tcg_global_mem_new(cpu_env,
|
||||
hex_slot_cancelled = tcg_global_mem_new(tcg_env,
|
||||
offsetof(CPUHexagonState, slot_cancelled), "slot_cancelled");
|
||||
hex_llsc_addr = tcg_global_mem_new(cpu_env,
|
||||
hex_llsc_addr = tcg_global_mem_new(tcg_env,
|
||||
offsetof(CPUHexagonState, llsc_addr), "llsc_addr");
|
||||
hex_llsc_val = tcg_global_mem_new(cpu_env,
|
||||
hex_llsc_val = tcg_global_mem_new(tcg_env,
|
||||
offsetof(CPUHexagonState, llsc_val), "llsc_val");
|
||||
hex_llsc_val_i64 = tcg_global_mem_new_i64(cpu_env,
|
||||
hex_llsc_val_i64 = tcg_global_mem_new_i64(tcg_env,
|
||||
offsetof(CPUHexagonState, llsc_val_i64), "llsc_val_i64");
|
||||
for (i = 0; i < STORES_MAX; i++) {
|
||||
snprintf(store_addr_names[i], NAME_LEN, "store_addr_%d", i);
|
||||
hex_store_addr[i] = tcg_global_mem_new(cpu_env,
|
||||
hex_store_addr[i] = tcg_global_mem_new(tcg_env,
|
||||
offsetof(CPUHexagonState, mem_log_stores[i].va),
|
||||
store_addr_names[i]);
|
||||
|
||||
snprintf(store_width_names[i], NAME_LEN, "store_width_%d", i);
|
||||
hex_store_width[i] = tcg_global_mem_new(cpu_env,
|
||||
hex_store_width[i] = tcg_global_mem_new(tcg_env,
|
||||
offsetof(CPUHexagonState, mem_log_stores[i].width),
|
||||
store_width_names[i]);
|
||||
|
||||
snprintf(store_val32_names[i], NAME_LEN, "store_val32_%d", i);
|
||||
hex_store_val32[i] = tcg_global_mem_new(cpu_env,
|
||||
hex_store_val32[i] = tcg_global_mem_new(tcg_env,
|
||||
offsetof(CPUHexagonState, mem_log_stores[i].data32),
|
||||
store_val32_names[i]);
|
||||
|
||||
snprintf(store_val64_names[i], NAME_LEN, "store_val64_%d", i);
|
||||
hex_store_val64[i] = tcg_global_mem_new_i64(cpu_env,
|
||||
hex_store_val64[i] = tcg_global_mem_new_i64(tcg_env,
|
||||
offsetof(CPUHexagonState, mem_log_stores[i].data64),
|
||||
store_val64_names[i]);
|
||||
}
|
||||
for (int i = 0; i < VSTORES_MAX; i++) {
|
||||
snprintf(vstore_addr_names[i], NAME_LEN, "vstore_addr_%d", i);
|
||||
hex_vstore_addr[i] = tcg_global_mem_new(cpu_env,
|
||||
hex_vstore_addr[i] = tcg_global_mem_new(tcg_env,
|
||||
offsetof(CPUHexagonState, vstore[i].va),
|
||||
vstore_addr_names[i]);
|
||||
|
||||
snprintf(vstore_size_names[i], NAME_LEN, "vstore_size_%d", i);
|
||||
hex_vstore_size[i] = tcg_global_mem_new(cpu_env,
|
||||
hex_vstore_size[i] = tcg_global_mem_new(tcg_env,
|
||||
offsetof(CPUHexagonState, vstore[i].size),
|
||||
vstore_size_names[i]);
|
||||
|
||||
snprintf(vstore_pending_names[i], NAME_LEN, "vstore_pending_%d", i);
|
||||
hex_vstore_pending[i] = tcg_global_mem_new(cpu_env,
|
||||
hex_vstore_pending[i] = tcg_global_mem_new(tcg_env,
|
||||
offsetof(CPUHexagonState, vstore_pending[i]),
|
||||
vstore_pending_names[i]);
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue