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tcg: Rename cpu_env to tcg_env

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Allow the name 'cpu_env' to be used for something else.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-09-13 16:37:36 -07:00
parent a953b5fa15
commit ad75a51e84
91 changed files with 3818 additions and 3819 deletions
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24
target/arm/tcg/translate-m-nocp.c
View file

@ -85,9 +85,9 @@ static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_VLSTM *a)
fptr = load_reg(s, a->rn);
if (a->l) {
gen_helper_v7m_vlldm(cpu_env, fptr);
gen_helper_v7m_vlldm(tcg_env, fptr);
} else {
gen_helper_v7m_vlstm(cpu_env, fptr);
gen_helper_v7m_vlstm(tcg_env, fptr);
}
clear_eci_state(s);
@ -322,7 +322,7 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,
switch (regno) {
case ARM_VFP_FPSCR:
tmp = loadfn(s, opaque, true);
gen_helper_vfp_set_fpscr(cpu_env, tmp);
gen_helper_vfp_set_fpscr(tcg_env, tmp);
gen_lookup_tb(s);
break;
case ARM_VFP_FPSCR_NZCVQC:
@ -391,7 +391,7 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,
R_V7M_CONTROL_SFPA_SHIFT, 1);
store_cpu_field(control, v7m.control[M_REG_S]);
tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK);
gen_helper_vfp_set_fpscr(cpu_env, tmp);
gen_helper_vfp_set_fpscr(tcg_env, tmp);
s->base.is_jmp = DISAS_UPDATE_NOCHAIN;
break;
}
@ -451,12 +451,12 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno,
switch (regno) {
case ARM_VFP_FPSCR:
tmp = tcg_temp_new_i32();
gen_helper_vfp_get_fpscr(tmp, cpu_env);
gen_helper_vfp_get_fpscr(tmp, tcg_env);
storefn(s, opaque, tmp, true);
break;
case ARM_VFP_FPSCR_NZCVQC:
tmp = tcg_temp_new_i32();
gen_helper_vfp_get_fpscr(tmp, cpu_env);
gen_helper_vfp_get_fpscr(tmp, tcg_env);
tcg_gen_andi_i32(tmp, tmp, FPCR_NZCVQC_MASK);
storefn(s, opaque, tmp, true);
break;
@ -475,7 +475,7 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno,
/* Bits [27:0] from FPSCR, bit [31] from CONTROL.SFPA */
tmp = tcg_temp_new_i32();
sfpa = tcg_temp_new_i32();
gen_helper_vfp_get_fpscr(tmp, cpu_env);
gen_helper_vfp_get_fpscr(tmp, tcg_env);
tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK);
control = load_cpu_field(v7m.control[M_REG_S]);
tcg_gen_andi_i32(sfpa, control, R_V7M_CONTROL_SFPA_MASK);
@ -493,7 +493,7 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno,
tcg_gen_andi_i32(control, control, ~R_V7M_CONTROL_SFPA_MASK);
store_cpu_field(control, v7m.control[M_REG_S]);
fpscr = load_cpu_field(v7m.fpdscr[M_REG_NS]);
gen_helper_vfp_set_fpscr(cpu_env, fpscr);
gen_helper_vfp_set_fpscr(tcg_env, fpscr);
lookup_tb = true;
break;
}
@ -528,7 +528,7 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno,
tmp = tcg_temp_new_i32();
sfpa = tcg_temp_new_i32();
fpscr = tcg_temp_new_i32();
gen_helper_vfp_get_fpscr(fpscr, cpu_env);
gen_helper_vfp_get_fpscr(fpscr, tcg_env);
tcg_gen_andi_i32(tmp, fpscr, ~FPCR_NZCV_MASK);
control = load_cpu_field(v7m.control[M_REG_S]);
tcg_gen_andi_i32(sfpa, control, R_V7M_CONTROL_SFPA_MASK);
@ -540,7 +540,7 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno,
fpdscr = load_cpu_field(v7m.fpdscr[M_REG_NS]);
tcg_gen_movcond_i32(TCG_COND_EQ, fpscr, sfpa, tcg_constant_i32(0),
fpdscr, fpscr);
gen_helper_vfp_set_fpscr(cpu_env, fpscr);
gen_helper_vfp_set_fpscr(tcg_env, fpscr);
break;
}
case ARM_VFP_VPR:
@ -643,7 +643,7 @@ static void fp_sysreg_to_memory(DisasContext *s, void *opaque, TCGv_i32 value,
}
if (s->v8m_stackcheck && a->rn == 13 && a->w) {
gen_helper_v8m_stackcheck(cpu_env, addr);
gen_helper_v8m_stackcheck(tcg_env, addr);
}
if (do_access) {
@ -682,7 +682,7 @@ static TCGv_i32 memory_to_fp_sysreg(DisasContext *s, void *opaque,
}
if (s->v8m_stackcheck && a->rn == 13 && a->w) {
gen_helper_v8m_stackcheck(cpu_env, addr);
gen_helper_v8m_stackcheck(tcg_env, addr);
}
if (do_access) {