motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-04 00:03:54 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

target/loongarch: Implement LSX fpu arith instructions

Browse source 
This patch includes:
- VF{ADD/SUB/MUL/DIV}.{S/D};
- VF{MADD/MSUB/NMADD/NMSUB}.{S/D};
- VF{MAX/MIN}.{S/D};
- VF{MAXA/MINA}.{S/D};
- VFLOGB.{S/D};
- VFCLASS.{S/D};
- VF{SQRT/RECIP/RSQRT}.{S/D}.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-34-gaosong@loongson.cn>
This commit is contained in:
Song Gao 2023-05-04 20:27:59 +08:00
parent ac95a0b975
commit aca67472d2
No known key found for this signature in database
GPG key ID: 40A2FFF239263EDF
8 changed files with 377 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

43
target/loongarch/insns.decode
View file

@ -493,6 +493,7 @@ dbcl 0000 00000010 10101 ............... @i15
&vv vd vj
&vvv vd vj vk
&vv_i vd vj imm
&vvvv vd vj vk va
#
# LSX Formats
@ -506,6 +507,7 @@ dbcl 0000 00000010 10101 ............... @i15
@vv_ui7 .... ........ ... imm:7 vj:5 vd:5 &vv_i
@vv_ui8 .... ........ .. imm:8 vj:5 vd:5 &vv_i
@vv_i5 .... ........ ..... imm:s5 vj:5 vd:5 &vv_i
@vvvv .... ........ va:5 vk:5 vj:5 vd:5 &vvvv
vadd_b 0111 00000000 10100 ..... ..... ..... @vvv
vadd_h 0111 00000000 10101 ..... ..... ..... @vvv
@ -1003,3 +1005,44 @@ vfrstp_b 0111 00010010 10110 ..... ..... ..... @vvv
vfrstp_h 0111 00010010 10111 ..... ..... ..... @vvv
vfrstpi_b 0111 00101001 10100 ..... ..... ..... @vv_ui5
vfrstpi_h 0111 00101001 10101 ..... ..... ..... @vv_ui5
vfadd_s 0111 00010011 00001 ..... ..... ..... @vvv
vfadd_d 0111 00010011 00010 ..... ..... ..... @vvv
vfsub_s 0111 00010011 00101 ..... ..... ..... @vvv
vfsub_d 0111 00010011 00110 ..... ..... ..... @vvv
vfmul_s 0111 00010011 10001 ..... ..... ..... @vvv
vfmul_d 0111 00010011 10010 ..... ..... ..... @vvv
vfdiv_s 0111 00010011 10101 ..... ..... ..... @vvv
vfdiv_d 0111 00010011 10110 ..... ..... ..... @vvv
vfmadd_s 0000 10010001 ..... ..... ..... ..... @vvvv
vfmadd_d 0000 10010010 ..... ..... ..... ..... @vvvv
vfmsub_s 0000 10010101 ..... ..... ..... ..... @vvvv
vfmsub_d 0000 10010110 ..... ..... ..... ..... @vvvv
vfnmadd_s 0000 10011001 ..... ..... ..... ..... @vvvv
vfnmadd_d 0000 10011010 ..... ..... ..... ..... @vvvv
vfnmsub_s 0000 10011101 ..... ..... ..... ..... @vvvv
vfnmsub_d 0000 10011110 ..... ..... ..... ..... @vvvv
vfmax_s 0111 00010011 11001 ..... ..... ..... @vvv
vfmax_d 0111 00010011 11010 ..... ..... ..... @vvv
vfmin_s 0111 00010011 11101 ..... ..... ..... @vvv
vfmin_d 0111 00010011 11110 ..... ..... ..... @vvv
vfmaxa_s 0111 00010100 00001 ..... ..... ..... @vvv
vfmaxa_d 0111 00010100 00010 ..... ..... ..... @vvv
vfmina_s 0111 00010100 00101 ..... ..... ..... @vvv
vfmina_d 0111 00010100 00110 ..... ..... ..... @vvv
vflogb_s 0111 00101001 11001 10001 ..... ..... @vv
vflogb_d 0111 00101001 11001 10010 ..... ..... @vv
vfclass_s 0111 00101001 11001 10101 ..... ..... @vv
vfclass_d 0111 00101001 11001 10110 ..... ..... @vv
vfsqrt_s 0111 00101001 11001 11001 ..... ..... @vv
vfsqrt_d 0111 00101001 11001 11010 ..... ..... @vv
vfrecip_s 0111 00101001 11001 11101 ..... ..... @vv
vfrecip_d 0111 00101001 11001 11110 ..... ..... @vv
vfrsqrt_s 0111 00101001 11010 00001 ..... ..... @vv
vfrsqrt_d 0111 00101001 11010 00010 ..... ..... @vv