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target/mips: Rename cpu_supports_FEAT() as cpu_type_supports_FEAT()
As cpu_supports_isa() / cpu_supports_cps_smp() take a 'cpu_type' name argument, rename them cpu_type_supports_FEAT(). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20201207215257.4004222-2-f4bug@amsat.org>
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4 changed files with 8 additions and 8 deletions
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@ -1286,8 +1286,8 @@ int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
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#define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX
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#define CPU_RESOLVING_TYPE TYPE_MIPS_CPU
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bool cpu_supports_cps_smp(const char *cpu_type);
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bool cpu_supports_isa(const char *cpu_type, uint64_t isa);
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bool cpu_type_supports_cps_smp(const char *cpu_type);
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bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa);
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void cpu_set_exception_base(int vp_index, target_ulong address);
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/* mips_int.c */
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@ -31770,13 +31770,13 @@ void cpu_mips_realize_env(CPUMIPSState *env)
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mvp_init(env, env->cpu_model);
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}
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bool cpu_supports_cps_smp(const char *cpu_type)
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bool cpu_type_supports_cps_smp(const char *cpu_type)
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{
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const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type));
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return (mcc->cpu_def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0;
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}
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bool cpu_supports_isa(const char *cpu_type, uint64_t isa)
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bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa)
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{
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const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type));
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return (mcc->cpu_def->insn_flags & isa) != 0;
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