motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-22 01:21:53 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

hw/sh4: Coding style: Add missing braces

Browse source 
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Message-Id: <b53a8cbcf57207fbd6408db1007b3e82008d60f7.1635541329.git.balaton@eik.bme.hu>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
This commit is contained in:
BALATON Zoltan 2021-10-29 23:02:09 +02:00 • committed by Philippe Mathieu-Daudé
parent f94bff1337
commit ac3c9e74c1
6 changed files with 118 additions and 81 deletions
Download patch file Download diff file Expand all files Collapse all files

48
hw/char/sh_serial.c
View file

@ -103,8 +103,9 @@ static void sh_serial_write(void *opaque, hwaddr offs,
case 0x08: /* SCR */ case 0x08: /* SCR */
/* TODO : For SH7751, SCIF mask should be 0xfb. */ /* TODO : For SH7751, SCIF mask should be 0xfb. */
s->scr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0xfa : 0xff); s->scr = val & ((s->feat & SH_SERIAL_FEAT_SCIF) ? 0xfa : 0xff);
if (!(val & (1 << 5))) if (!(val & (1 << 5))) {
s->flags |= SH_SERIAL_FLAG_TEND; s->flags |= SH_SERIAL_FLAG_TEND;
}
if ((s->feat & SH_SERIAL_FEAT_SCIF) && s->txi) { if ((s->feat & SH_SERIAL_FEAT_SCIF) && s->txi) {
qemu_set_irq(s->txi, val & (1 << 7)); qemu_set_irq(s->txi, val & (1 << 7));
} }
@ -133,16 +134,21 @@ static void sh_serial_write(void *opaque, hwaddr offs,
if (s->feat & SH_SERIAL_FEAT_SCIF) { if (s->feat & SH_SERIAL_FEAT_SCIF) {
switch (offs) { switch (offs) {
case 0x10: /* FSR */ case 0x10: /* FSR */
if (!(val & (1 << 6))) if (!(val & (1 << 6))) {
s->flags &= ~SH_SERIAL_FLAG_TEND; s->flags &= ~SH_SERIAL_FLAG_TEND;
if (!(val & (1 << 5))) }
if (!(val & (1 << 5))) {
s->flags &= ~SH_SERIAL_FLAG_TDE; s->flags &= ~SH_SERIAL_FLAG_TDE;
if (!(val & (1 << 4))) }
if (!(val & (1 << 4))) {
s->flags &= ~SH_SERIAL_FLAG_BRK; s->flags &= ~SH_SERIAL_FLAG_BRK;
if (!(val & (1 << 1))) }
if (!(val & (1 << 1))) {
s->flags &= ~SH_SERIAL_FLAG_RDF; s->flags &= ~SH_SERIAL_FLAG_RDF;
if (!(val & (1 << 0))) }
if (!(val & (1 << 0))) {
s->flags &= ~SH_SERIAL_FLAG_DR; s->flags &= ~SH_SERIAL_FLAG_DR;
}
if (!(val & (1 << 1)) || !(val & (1 << 0))) { if (!(val & (1 << 1)) || !(val & (1 << 0))) {
if (s->rxi) { if (s->rxi) {
@ -231,30 +237,38 @@ static uint64_t sh_serial_read(void *opaque, hwaddr offs,
break; break;
case 0x10: /* FSR */ case 0x10: /* FSR */
ret = 0; ret = 0;
if (s->flags & SH_SERIAL_FLAG_TEND) if (s->flags & SH_SERIAL_FLAG_TEND) {
ret |= (1 << 6); ret |= (1 << 6);
if (s->flags & SH_SERIAL_FLAG_TDE) }
if (s->flags & SH_SERIAL_FLAG_TDE) {
ret |= (1 << 5); ret |= (1 << 5);
if (s->flags & SH_SERIAL_FLAG_BRK) }
if (s->flags & SH_SERIAL_FLAG_BRK) {
ret |= (1 << 4); ret |= (1 << 4);
if (s->flags & SH_SERIAL_FLAG_RDF) }
if (s->flags & SH_SERIAL_FLAG_RDF) {
ret |= (1 << 1); ret |= (1 << 1);
if (s->flags & SH_SERIAL_FLAG_DR) }
if (s->flags & SH_SERIAL_FLAG_DR) {
ret |= (1 << 0); ret |= (1 << 0);
}
if (s->scr & (1 << 5)) if (s->scr & (1 << 5)) {
s->flags |= SH_SERIAL_FLAG_TDE | SH_SERIAL_FLAG_TEND; s->flags |= SH_SERIAL_FLAG_TDE | SH_SERIAL_FLAG_TEND;
}
break; break;
case 0x14: case 0x14:
if (s->rx_cnt > 0) { if (s->rx_cnt > 0) {
ret = s->rx_fifo[s->rx_tail++]; ret = s->rx_fifo[s->rx_tail++];
s->rx_cnt--; s->rx_cnt--;
if (s->rx_tail == SH_RX_FIFO_LENGTH) if (s->rx_tail == SH_RX_FIFO_LENGTH) {
s->rx_tail = 0; s->rx_tail = 0;
if (s->rx_cnt < s->rtrg) }
if (s->rx_cnt < s->rtrg) {
s->flags &= ~SH_SERIAL_FLAG_RDF; s->flags &= ~SH_SERIAL_FLAG_RDF;
} }
}
break; break;
case 0x18: case 0x18:
ret = s->fcr; ret = s->fcr;
@ -308,8 +322,9 @@ static int sh_serial_can_receive(sh_serial_state *s)
static void sh_serial_receive_break(sh_serial_state *s) static void sh_serial_receive_break(sh_serial_state *s)
{ {
if (s->feat & SH_SERIAL_FEAT_SCIF) if (s->feat & SH_SERIAL_FEAT_SCIF) {
s->sr |= (1 << 4); s->sr |= (1 << 4);
}
} }
static int sh_serial_can_receive1(void *opaque) static int sh_serial_can_receive1(void *opaque)
@ -361,8 +376,9 @@ static void sh_serial_receive1(void *opaque, const uint8_t *buf, int size)
static void sh_serial_event(void *opaque, QEMUChrEvent event) static void sh_serial_event(void *opaque, QEMUChrEvent event)
{ {
sh_serial_state *s = opaque; sh_serial_state *s = opaque;
if (event == CHR_EVENT_BREAK) if (event == CHR_EVENT_BREAK) {
sh_serial_receive_break(s); sh_serial_receive_break(s);
}
} }
static const MemoryRegionOps sh_serial_ops = { static const MemoryRegionOps sh_serial_ops = {

81
hw/intc/sh_intc.c
View file

@ -26,23 +26,23 @@ void sh_intc_toggle_source(struct intc_source *source,
int pending_changed = 0; int pending_changed = 0;
int old_pending; int old_pending;
if ((source->enable_count == source->enable_max) && (enable_adj == -1)) if ((source->enable_count == source->enable_max) && (enable_adj == -1)) {
enable_changed = -1; enable_changed = -1;
}
source->enable_count += enable_adj; source->enable_count += enable_adj;
if (source->enable_count == source->enable_max) if (source->enable_count == source->enable_max) {
enable_changed = 1; enable_changed = 1;
}
source->asserted += assert_adj; source->asserted += assert_adj;
old_pending = source->pending; old_pending = source->pending;
source->pending = source->asserted && source->pending = source->asserted &&
(source->enable_count == source->enable_max); (source->enable_count == source->enable_max);
if (old_pending != source->pending) if (old_pending != source->pending) {
pending_changed = 1; pending_changed = 1;
}
if (pending_changed) { if (pending_changed) {
if (source->pending) { if (source->pending) {
source->parent->pending++; source->parent->pending++;
@ -79,10 +79,11 @@ static void sh_intc_set_irq(void *opaque, int n, int level)
struct intc_desc *desc = opaque; struct intc_desc *desc = opaque;
struct intc_source *source = &(desc->sources[n]); struct intc_source *source = &(desc->sources[n]);
if (level && !source->asserted) if (level && !source->asserted) {
sh_intc_toggle_source(source, 0, 1); sh_intc_toggle_source(source, 0, 1);
else if (!level && source->asserted) } else if (!level && source->asserted) {
sh_intc_toggle_source(source, 0, -1); sh_intc_toggle_source(source, 0, -1);
}
} }
int sh_intc_get_pending_vector(struct intc_desc *desc, int imask) int sh_intc_get_pending_vector(struct intc_desc *desc, int imask)
@ -126,16 +127,18 @@ static unsigned int sh_intc_mode(unsigned long address,
return INTC_MODE_NONE; return INTC_MODE_NONE;
if (set_reg && clr_reg) { if (set_reg && clr_reg) {
if (address == INTC_A7(set_reg)) if (address == INTC_A7(set_reg)) {
return INTC_MODE_DUAL_SET; return INTC_MODE_DUAL_SET;
else } else {
return INTC_MODE_DUAL_CLR; return INTC_MODE_DUAL_CLR;
} }
}
if (set_reg) if (set_reg) {
return INTC_MODE_ENABLE_REG; return INTC_MODE_ENABLE_REG;
else } else {
return INTC_MODE_MASK_REG; return INTC_MODE_MASK_REG;
}
} }
static void sh_intc_locate(struct intc_desc *desc, static void sh_intc_locate(struct intc_desc *desc,
@ -155,9 +158,9 @@ static void sh_intc_locate(struct intc_desc *desc,
struct intc_mask_reg *mr = desc->mask_regs + i; struct intc_mask_reg *mr = desc->mask_regs + i;
mode = sh_intc_mode(address, mr->set_reg, mr->clr_reg); mode = sh_intc_mode(address, mr->set_reg, mr->clr_reg);
if (mode == INTC_MODE_NONE) if (mode == INTC_MODE_NONE) {
continue; continue;
}
*modep = mode; *modep = mode;
*datap = &mr->value; *datap = &mr->value;
*enums = mr->enum_ids; *enums = mr->enum_ids;
@ -172,9 +175,9 @@ static void sh_intc_locate(struct intc_desc *desc,
struct intc_prio_reg *pr = desc->prio_regs + i; struct intc_prio_reg *pr = desc->prio_regs + i;
mode = sh_intc_mode(address, pr->set_reg, pr->clr_reg); mode = sh_intc_mode(address, pr->set_reg, pr->clr_reg);
if (mode == INTC_MODE_NONE) if (mode == INTC_MODE_NONE) {
continue; continue;
}
*modep = mode | INTC_MODE_IS_PRIO; *modep = mode | INTC_MODE_IS_PRIO;
*datap = &pr->value; *datap = &pr->value;
*enums = pr->enum_ids; *enums = pr->enum_ids;
@ -192,9 +195,9 @@ static void sh_intc_toggle_mask(struct intc_desc *desc, intc_enum id,
{ {
struct intc_source *source = desc->sources + id; struct intc_source *source = desc->sources + id;
if (!id) if (!id) {
return; return;
}
if (!source->next_enum_id && (!source->enable_max || !source->vect)) { if (!source->next_enum_id && (!source->enable_max || !source->vect)) {
#ifdef DEBUG_INTC_SOURCES #ifdef DEBUG_INTC_SOURCES
printf("sh_intc: reserved interrupt source %d modified\n", id); printf("sh_intc: reserved interrupt source %d modified\n", id);
@ -202,9 +205,9 @@ static void sh_intc_toggle_mask(struct intc_desc *desc, intc_enum id,
return; return;
} }
if (source->vect) if (source->vect) {
sh_intc_toggle_source(source, enable ? 1 : -1, 0); sh_intc_toggle_source(source, enable ? 1 : -1, 0);
}
#ifdef DEBUG_INTC #ifdef DEBUG_INTC
else { else {
printf("setting interrupt group %d to %d\n", id, !!enable); printf("setting interrupt group %d to %d\n", id, !!enable);
@ -276,8 +279,9 @@ static void sh_intc_write(void *opaque, hwaddr offset,
for (k = 0; k <= first; k++) { for (k = 0; k <= first; k++) {
mask = ((1 << width) - 1) << ((first - k) * width); mask = ((1 << width) - 1) << ((first - k) * width);
if ((*valuep & mask) == (value & mask)) if ((*valuep & mask) == (value & mask)) {
continue; continue;
}
#if 0 #if 0
printf("k = %d, first = %d, enum = %d, mask = 0x%08x\n", printf("k = %d, first = %d, enum = %d, mask = 0x%08x\n",
k, first, enum_ids[k], (unsigned int)mask); k, first, enum_ids[k], (unsigned int)mask);
@ -300,9 +304,9 @@ static const MemoryRegionOps sh_intc_ops = {
struct intc_source *sh_intc_source(struct intc_desc *desc, intc_enum id) struct intc_source *sh_intc_source(struct intc_desc *desc, intc_enum id)
{ {
if (id) if (id) {
return desc->sources + id; return desc->sources + id;
}
return NULL; return NULL;
} }
@ -351,45 +355,48 @@ static void sh_intc_register_source(struct intc_desc *desc,
struct intc_mask_reg *mr = desc->mask_regs + i; struct intc_mask_reg *mr = desc->mask_regs + i;
for (k = 0; k < ARRAY_SIZE(mr->enum_ids); k++) { for (k = 0; k < ARRAY_SIZE(mr->enum_ids); k++) {
if (mr->enum_ids[k] != source) if (mr->enum_ids[k] != source) {
continue; continue;
}
s = sh_intc_source(desc, mr->enum_ids[k]); s = sh_intc_source(desc, mr->enum_ids[k]);
if (s) if (s) {
s->enable_max++; s->enable_max++;
} }
} }
} }
}
if (desc->prio_regs) { if (desc->prio_regs) {
for (i = 0; i < desc->nr_prio_regs; i++) { for (i = 0; i < desc->nr_prio_regs; i++) {
struct intc_prio_reg *pr = desc->prio_regs + i; struct intc_prio_reg *pr = desc->prio_regs + i;
for (k = 0; k < ARRAY_SIZE(pr->enum_ids); k++) { for (k = 0; k < ARRAY_SIZE(pr->enum_ids); k++) {
if (pr->enum_ids[k] != source) if (pr->enum_ids[k] != source) {
continue; continue;
}
s = sh_intc_source(desc, pr->enum_ids[k]); s = sh_intc_source(desc, pr->enum_ids[k]);
if (s) if (s) {
s->enable_max++; s->enable_max++;
} }
} }
} }
}
if (groups) { if (groups) {
for (i = 0; i < nr_groups; i++) { for (i = 0; i < nr_groups; i++) {
struct intc_group *gr = groups + i; struct intc_group *gr = groups + i;
for (k = 0; k < ARRAY_SIZE(gr->enum_ids); k++) { for (k = 0; k < ARRAY_SIZE(gr->enum_ids); k++) {
if (gr->enum_ids[k] != source) if (gr->enum_ids[k] != source) {
continue; continue;
}
s = sh_intc_source(desc, gr->enum_ids[k]); s = sh_intc_source(desc, gr->enum_ids[k]);
if (s) if (s) {
s->enable_max++; s->enable_max++;
} }
} }
} }
}
} }
@ -425,9 +432,9 @@ void sh_intc_register_sources(struct intc_desc *desc,
s->next_enum_id = gr->enum_ids[0]; s->next_enum_id = gr->enum_ids[0];
for (k = 1; k < ARRAY_SIZE(gr->enum_ids); k++) { for (k = 1; k < ARRAY_SIZE(gr->enum_ids); k++) {
if (!gr->enum_ids[k]) if (!gr->enum_ids[k]) {
continue; continue;
}
s = sh_intc_source(desc, gr->enum_ids[k - 1]); s = sh_intc_source(desc, gr->enum_ids[k - 1]);
s->next_enum_id = gr->enum_ids[k]; s->next_enum_id = gr->enum_ids[k];
} }
@ -512,11 +519,11 @@ void sh_intc_set_irl(void *opaque, int n, int level)
struct intc_source *s = opaque; struct intc_source *s = opaque;
int i, irl = level ^ 15; int i, irl = level ^ 15;
for (i = 0; (s = sh_intc_source(s->parent, s->next_enum_id)); i++) { for (i = 0; (s = sh_intc_source(s->parent, s->next_enum_id)); i++) {
if (i == irl) if (i == irl) {
sh_intc_toggle_source(s, s->enable_count ? 0 : 1, sh_intc_toggle_source(s, s->enable_count ? 0 : 1,
s->asserted ? 0 : 1); s->asserted ? 0 : 1);
else } else if (s->asserted) {
if (s->asserted)
sh_intc_toggle_source(s, 0, -1); sh_intc_toggle_source(s, 0, -1);
} }
}
} }

13
hw/sh4/r2d.c
View file

@ -114,20 +114,23 @@ static const struct { short irl; uint16_t msk; } irqtab[NR_IRQS] = {
static void update_irl(r2d_fpga_t *fpga) static void update_irl(r2d_fpga_t *fpga)
{ {
int i, irl = 15; int i, irl = 15;
for (i = 0; i < NR_IRQS; i++) for (i = 0; i < NR_IRQS; i++) {
if (fpga->irlmon & fpga->irlmsk & irqtab[i].msk) if ((fpga->irlmon & fpga->irlmsk & irqtab[i].msk) &&
if (irqtab[i].irl < irl) irqtab[i].irl < irl) {
irl = irqtab[i].irl; irl = irqtab[i].irl;
}
}
qemu_set_irq(fpga->irl, irl ^ 15); qemu_set_irq(fpga->irl, irl ^ 15);
} }
static void r2d_fpga_irq_set(void *opaque, int n, int level) static void r2d_fpga_irq_set(void *opaque, int n, int level)
{ {
r2d_fpga_t *fpga = opaque; r2d_fpga_t *fpga = opaque;
if (level) if (level) {
fpga->irlmon |= irqtab[n].msk; fpga->irlmon |= irqtab[n].msk;
else } else {
fpga->irlmon &= ~irqtab[n].msk; fpga->irlmon &= ~irqtab[n].msk;
}
update_irl(fpga); update_irl(fpga);
} }

24
hw/sh4/sh7750.c
View file

@ -153,8 +153,9 @@ static void porta_changed(SH7750State *s, uint16_t prev)
fprintf(stderr, "pdtra=0x%04x, pctra=0x%08x\n", s->pdtra, s->pctra); fprintf(stderr, "pdtra=0x%04x, pctra=0x%08x\n", s->pdtra, s->pctra);
#endif #endif
currenta = porta_lines(s); currenta = porta_lines(s);
if (currenta == prev) if (currenta == prev) {
return; return;
}
changes = currenta ^ prev; changes = currenta ^ prev;
for (i = 0; i < NB_DEVICES; i++) { for (i = 0; i < NB_DEVICES; i++) {
@ -167,8 +168,9 @@ static void porta_changed(SH7750State *s, uint16_t prev)
} }
} }
if (r) if (r) {
gen_port_interrupts(s); gen_port_interrupts(s);
}
} }
static void portb_changed(SH7750State *s, uint16_t prev) static void portb_changed(SH7750State *s, uint16_t prev)
@ -177,8 +179,9 @@ static void portb_changed(SH7750State *s, uint16_t prev)
int i, r = 0; int i, r = 0;
currentb = portb_lines(s); currentb = portb_lines(s);
if (currentb == prev) if (currentb == prev) {
return; return;
}
changes = currentb ^ prev; changes = currentb ^ prev;
for (i = 0; i < NB_DEVICES; i++) { for (i = 0; i < NB_DEVICES; i++) {
@ -191,8 +194,9 @@ static void portb_changed(SH7750State *s, uint16_t prev)
} }
} }
if (r) if (r) {
gen_port_interrupts(s); gen_port_interrupts(s);
}
} }
/* /*
@ -228,8 +232,9 @@ static uint32_t sh7750_mem_readw(void *opaque, hwaddr addr)
case SH7750_BCR2_A7: case SH7750_BCR2_A7:
return s->bcr2; return s->bcr2;
case SH7750_BCR3_A7: case SH7750_BCR3_A7:
if (!has_bcr3_and_bcr4(s)) if (!has_bcr3_and_bcr4(s)) {
error_access("word read", addr); error_access("word read", addr);
}
return s->bcr3; return s->bcr3;
case SH7750_FRQCR_A7: case SH7750_FRQCR_A7:
return 0; return 0;
@ -263,8 +268,9 @@ static uint32_t sh7750_mem_readl(void *opaque, hwaddr addr)
case SH7750_BCR1_A7: case SH7750_BCR1_A7:
return s->bcr1; return s->bcr1;
case SH7750_BCR4_A7: case SH7750_BCR4_A7:
if (!has_bcr3_and_bcr4(s)) if (!has_bcr3_and_bcr4(s)) {
error_access("long read", addr); error_access("long read", addr);
}
return s->bcr4; return s->bcr4;
case SH7750_WCR1_A7: case SH7750_WCR1_A7:
case SH7750_WCR2_A7: case SH7750_WCR2_A7:
@ -332,8 +338,9 @@ static void sh7750_mem_writew(void *opaque, hwaddr addr,
s->bcr2 = mem_value; s->bcr2 = mem_value;
return; return;
case SH7750_BCR3_A7: case SH7750_BCR3_A7:
if (!has_bcr3_and_bcr4(s)) if (!has_bcr3_and_bcr4(s)) {
error_access("word write", addr); error_access("word write", addr);
}
s->bcr3 = mem_value; s->bcr3 = mem_value;
return; return;
case SH7750_PCR_A7: case SH7750_PCR_A7:
@ -384,8 +391,9 @@ static void sh7750_mem_writel(void *opaque, hwaddr addr,
s->bcr1 = mem_value; s->bcr1 = mem_value;
return; return;
case SH7750_BCR4_A7: case SH7750_BCR4_A7:
if (!has_bcr3_and_bcr4(s)) if (!has_bcr3_and_bcr4(s)) {
error_access("long write", addr); error_access("long write", addr);
}
s->bcr4 = mem_value; s->bcr4 = mem_value;
return; return;
case SH7750_WCR1_A7: case SH7750_WCR1_A7:

3
hw/sh4/sh7750_regnames.c
View file

@ -90,9 +90,10 @@ const char *regname(uint32_t addr)
unsigned int i; unsigned int i;
for (i = 0; regnames[i].regaddr != (uint32_t)-1; i++) { for (i = 0; regnames[i].regaddr != (uint32_t)-1; i++) {
if (regnames[i].regaddr == addr) if (regnames[i].regaddr == addr) {
return regnames[i].regname; return regnames[i].regname;
} }
}
return "<unknown reg>"; return "<unknown reg>";
} }

22
hw/timer/sh_timer.c
View file

@ -54,9 +54,9 @@ static void sh_timer_update(sh_timer_state *s)
{ {
int new_level = s->int_level && (s->tcr & TIMER_TCR_UNIE); int new_level = s->int_level && (s->tcr & TIMER_TCR_UNIE);
if (new_level != s->old_level) if (new_level != s->old_level) {
qemu_set_irq(s->irq, new_level); qemu_set_irq(s->irq, new_level);
}
s->old_level = s->int_level; s->old_level = s->int_level;
s->int_level = new_level; s->int_level = new_level;
} }
@ -73,8 +73,9 @@ static uint32_t sh_timer_read(void *opaque, hwaddr offset)
case OFFSET_TCR: case OFFSET_TCR:
return s->tcr | (s->int_level ? TIMER_TCR_UNF : 0); return s->tcr | (s->int_level ? TIMER_TCR_UNF : 0);
case OFFSET_TCPR: case OFFSET_TCPR:
if (s->feat & TIMER_FEAT_CAPT) if (s->feat & TIMER_FEAT_CAPT) {
return s->tcpr; return s->tcpr;
}
/* fall through */ /* fall through */
default: default:
hw_error("sh_timer_read: Bad offset %x\n", (int)offset); hw_error("sh_timer_read: Bad offset %x\n", (int)offset);
@ -279,17 +280,18 @@ static uint64_t tmu012_read(void *opaque, hwaddr offset,
return sh_timer_read(s->timer[2], offset - 0x20); return sh_timer_read(s->timer[2], offset - 0x20);
} }
if (offset >= 0x14) if (offset >= 0x14) {
return sh_timer_read(s->timer[1], offset - 0x14); return sh_timer_read(s->timer[1], offset - 0x14);
}
if (offset >= 0x08) if (offset >= 0x08) {
return sh_timer_read(s->timer[0], offset - 0x08); return sh_timer_read(s->timer[0], offset - 0x08);
}
if (offset == 4) if (offset == 4) {
return s->tstr; return s->tstr;
}
if ((s->feat & TMU012_FEAT_TOCR) && offset == 0) if ((s->feat & TMU012_FEAT_TOCR) && offset == 0) {
return s->tocr; return s->tocr;
}
hw_error("tmu012_write: Bad offset %x\n", (int)offset); hw_error("tmu012_write: Bad offset %x\n", (int)offset);
return 0; return 0;