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gdbstub: Use GDBFeature for gdb_register_coprocessor

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This is a tree-wide change to introduce GDBFeature parameter to
gdb_register_coprocessor(). The new parameter just replaces num_regs
and xml parameters for now. GDBFeature will be utilized to simplify XML
lookup in a following change.

Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Acked-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20231213-gdb-v17-4-777047380591@daynix.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240227144335.1196131-9-alex.bennee@linaro.org>
This commit is contained in:
Akihiko Odaki 2024-02-27 14:43:14 +00:00 • committed by Alex Bennée
parent 33a24910ae
commit ac1e867100
10 changed files with 60 additions and 65 deletions
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20
target/riscv/gdbstub.c
View file

@ -311,28 +311,32 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
CPURISCVState *env = &cpu->env;
if (env->misa_ext & RVD) {
gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
32, "riscv-64bit-fpu.xml", 0);
gdb_find_static_feature("riscv-64bit-fpu.xml"),
0);
} else if (env->misa_ext & RVF) {
gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
32, "riscv-32bit-fpu.xml", 0);
gdb_find_static_feature("riscv-32bit-fpu.xml"),
0);
}
if (env->misa_ext & RVV) {
gdb_register_coprocessor(cs, riscv_gdb_get_vector,
riscv_gdb_set_vector,
ricsv_gen_dynamic_vector_feature(cs, cs->gdb_num_regs)->num_regs,
"riscv-vector.xml", 0);
ricsv_gen_dynamic_vector_feature(cs, cs->gdb_num_regs),
0);
}
switch (mcc->misa_mxl_max) {
case MXL_RV32:
gdb_register_coprocessor(cs, riscv_gdb_get_virtual,
riscv_gdb_set_virtual,
1, "riscv-32bit-virtual.xml", 0);
gdb_find_static_feature("riscv-32bit-virtual.xml"),
0);
break;
case MXL_RV64:
case MXL_RV128:
gdb_register_coprocessor(cs, riscv_gdb_get_virtual,
riscv_gdb_set_virtual,
1, "riscv-64bit-virtual.xml", 0);
gdb_find_static_feature("riscv-64bit-virtual.xml"),
0);
break;
default:
g_assert_not_reached();
@ -340,7 +344,7 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
if (cpu->cfg.ext_zicsr) {
gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
riscv_gen_dynamic_csr_feature(cs, cs->gdb_num_regs)->num_regs,
"riscv-csr.xml", 0);
riscv_gen_dynamic_csr_feature(cs, cs->gdb_num_regs),
0);
}
}