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target/riscv: Remove privilege v1.9 specific CSR related code

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Qemu doesn't support RISC-V privilege specification v1.9. Remove the
remaining v1.9 specific references from the implementation.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20210319194534.2082397-2-atish.patra@wdc.com>
[Changes by AF:
 - Rebase on latest patches
 - Bump the vmstate_riscv_cpu version_id and minimum_version_id
 ]
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Atish Patra 2021-03-19 12:45:29 -07:00 • committed by Alistair Francis
parent e4f3ede95c
commit ac12b60103
7 changed files with 23 additions and 72 deletions
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42
target/riscv/csr.c
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@ -644,26 +644,6 @@ static int write_mcounteren(CPURISCVState *env, int csrno, target_ulong val)
return 0;
}
/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val)
{
if (env->priv_ver < PRIV_VERSION_1_11_0) {
return -RISCV_EXCP_ILLEGAL_INST;
}
*val = env->mcounteren;
return 0;
}
/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong val)
{
if (env->priv_ver < PRIV_VERSION_1_11_0) {
return -RISCV_EXCP_ILLEGAL_INST;
}
env->mcounteren = val;
return 0;
}
/* Machine Trap Handling */
static int read_mscratch(CPURISCVState *env, int csrno, target_ulong *val)
{
@ -701,15 +681,15 @@ static int write_mcause(CPURISCVState *env, int csrno, target_ulong val)
return 0;
}
static int read_mbadaddr(CPURISCVState *env, int csrno, target_ulong *val)
static int read_mtval(CPURISCVState *env, int csrno, target_ulong *val)
{
*val = env->mbadaddr;
*val = env->mtval;
return 0;
}
static int write_mbadaddr(CPURISCVState *env, int csrno, target_ulong val)
static int write_mtval(CPURISCVState *env, int csrno, target_ulong val)
{
env->mbadaddr = val;
env->mtval = val;
return 0;
}
@ -853,15 +833,15 @@ static int write_scause(CPURISCVState *env, int csrno, target_ulong val)
return 0;
}
static int read_sbadaddr(CPURISCVState *env, int csrno, target_ulong *val)
static int read_stval(CPURISCVState *env, int csrno, target_ulong *val)
{
*val = env->sbadaddr;
*val = env->stval;
return 0;
}
static int write_sbadaddr(CPURISCVState *env, int csrno, target_ulong val)
static int write_stval(CPURISCVState *env, int csrno, target_ulong val)
{
env->sbadaddr = val;
env->stval = val;
return 0;
}
@ -1419,13 +1399,11 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_MSTATUSH] = { "mstatush", any32, read_mstatush, write_mstatush },
[CSR_MSCOUNTEREN] = { "msounteren", any, read_mscounteren, write_mscounteren },
/* Machine Trap Handling */
[CSR_MSCRATCH] = { "mscratch", any, read_mscratch, write_mscratch },
[CSR_MEPC] = { "mepc", any, read_mepc, write_mepc },
[CSR_MCAUSE] = { "mcause", any, read_mcause, write_mcause },
[CSR_MBADADDR] = { "mbadaddr", any, read_mbadaddr, write_mbadaddr },
[CSR_MTVAL] = { "mtval", any, read_mtval, write_mtval },
[CSR_MIP] = { "mip", any, NULL, NULL, rmw_mip },
/* Supervisor Trap Setup */
@ -1438,7 +1416,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_SSCRATCH] = { "sscratch", smode, read_sscratch, write_sscratch },
[CSR_SEPC] = { "sepc", smode, read_sepc, write_sepc },
[CSR_SCAUSE] = { "scause", smode, read_scause, write_scause },
[CSR_SBADADDR] = { "sbadaddr", smode, read_sbadaddr, write_sbadaddr },
[CSR_STVAL] = { "stval", smode, read_stval, write_stval },
[CSR_SIP] = { "sip", smode, NULL, NULL, rmw_sip },
/* Supervisor Protection and Translation */