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armv7m: Fix reads of CONTROL register bit 1
The v7m CONTROL register bit 1 is SPSEL, which indicates the stack being used. We were storing this information not in v7m.control but in the separate v7m.other_sp structure field. Unfortunately, the code handling reads of the CONTROL register didn't take account of this, and so if SPSEL was updated by an exception entry or exit then a subsequent guest read of CONTROL would get the wrong value. Using a separate structure field doesn't really gain us anything in efficiency, so drop this unnecessary complexity in favour of simply storing all the bits in v7m.control. This is a migration compatibility break for M profile CPUs only. Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1484937883-1068-6-git-send-email-peter.maydell@linaro.org [PMM: rewrote commit message; use deposit32(); use FIELD to define constants for masking and shifting of CONTROL register fields ] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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4 changed files with 32 additions and 17 deletions
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@ -25,6 +25,8 @@
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#ifndef TARGET_ARM_INTERNALS_H
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#define TARGET_ARM_INTERNALS_H
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#include "hw/registerfields.h"
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/* register banks for CPU modes */
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#define BANK_USRSYS 0
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#define BANK_SVC 1
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@ -75,6 +77,11 @@ static const char * const excnames[] = {
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*/
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#define GTIMER_SCALE 16
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/* Bit definitions for the v7M CONTROL register */
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FIELD(V7M_CONTROL, NPRIV, 0, 1)
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FIELD(V7M_CONTROL, SPSEL, 1, 1)
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FIELD(V7M_CONTROL, FPCA, 2, 1)
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/*
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* For AArch64, map a given EL to an index in the banked_spsr array.
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* Note that this mapping and the AArch32 mapping defined in bank_number()
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