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aspeed/i2c: Check SRAM enablement on AST2500

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The SRAM must be enabled before using the Buffer Pool mode or the DMA
mode. This is not required on other SoCs.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Tested-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20191119141211.25716-3-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Cédric Le Goater 2019-11-19 15:11:56 +01:00 • committed by Peter Maydell
parent 6054fc73e8
commit aab90b1cac
2 changed files with 40 additions and 0 deletions
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3
include/hw/i2c/aspeed_i2c.h
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@ -61,6 +61,7 @@ typedef struct AspeedI2CState {
qemu_irq irq;
uint32_t intr_status;
uint32_t ctrl_global;
MemoryRegion pool_iomem;
uint8_t pool[ASPEED_I2C_MAX_POOL_SIZE];
@ -83,6 +84,8 @@ typedef struct AspeedI2CClass {
uint64_t pool_size;
hwaddr pool_base;
uint8_t *(*bus_pool_base)(AspeedI2CBus *);
bool check_sram;
} AspeedI2CClass;
I2CBus *aspeed_i2c_get_bus(DeviceState *dev, int busnr);