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ppc patch queue for 2023-05-28:

Browse source 
This queue includes several assorted fixes for PowerPC SPR
 emulation, a change in the default Pegasos2 CPU, the addition
 of AIL mode 3 for spapr, a PIC->CPU interrupt fix for prep and
 performance enhancements in fpu_helper.c.
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Merge tag 'pull-ppc-20230528' of https://gitlab.com/danielhb/qemu into staging

ppc patch queue for 2023-05-28:

This queue includes several assorted fixes for PowerPC SPR
emulation, a change in the default Pegasos2 CPU, the addition
of AIL mode 3 for spapr, a PIC->CPU interrupt fix for prep and
performance enhancements in fpu_helper.c.

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# gpg: Signature made Sun 28 May 2023 09:47:05 AM PDT
# gpg:                using EDDSA key 17EBFF9923D01800AF2838193CD9CA96DE033164
# gpg:                issuer "danielhb413@gmail.com"
# gpg: Good signature from "Daniel Henrique Barboza <danielhb413@gmail.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 17EB FF99 23D0 1800 AF28  3819 3CD9 CA96 DE03 3164

* tag 'pull-ppc-20230528' of https://gitlab.com/danielhb/qemu:
  ppc/pegasos2: Change default CPU to 7457
  target/ppc: Add POWER9 DD2.2 model
  target/ppc: Merge COMPUTE_CLASS and COMPUTE_FPRF
  pnv_lpc: disable reentrancy detection for lpc-hc
  target/ppc: Use SMT4 small core chip type in POWER9/10 PVRs
  hw/ppc/prep: Fix wiring of PIC -> CPU interrupt
  spapr: Add SPAPR_CAP_AIL_MODE_3 for AIL mode 3 support for H_SET_MODE hcall
  target/ppc: Alignment faults do not set DSISR in ISA v3.0 onward
  target/ppc: Fix width of some 32-bit SPRs
  target/ppc: Fix fallback to MFSS for MFFS* instructions on pre 3.0 ISAs

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-05-29 14:31:52 -07:00
commit aa9bbd8655
26 changed files with 201 additions and 129 deletions
Download patch file Download diff file Expand all files Collapse all files

2
include/hw/ppc/pnv.h
View file

@ -48,7 +48,7 @@ DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8,
DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER8NVL,
TYPE_PNV_CHIP_POWER8NVL)
#define TYPE_PNV_CHIP_POWER9 PNV_CHIP_TYPE_NAME("power9_v2.0")
#define TYPE_PNV_CHIP_POWER9 PNV_CHIP_TYPE_NAME("power9_v2.2")
DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER9,
TYPE_PNV_CHIP_POWER9)

4
include/hw/ppc/spapr.h
View file

@ -78,8 +78,10 @@ typedef enum {
#define SPAPR_CAP_FWNMI 0x0A
/* Support H_RPT_INVALIDATE */
#define SPAPR_CAP_RPT_INVALIDATE 0x0B
/* Support for AIL modes */
#define SPAPR_CAP_AIL_MODE_3 0x0C
/* Num Caps */
#define SPAPR_CAP_NUM (SPAPR_CAP_RPT_INVALIDATE + 1)
#define SPAPR_CAP_NUM (SPAPR_CAP_AIL_MODE_3 + 1)
/*
* Capability Values