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ppc/pnv: Set P10 core xscom region size to match hardware
The P10 core xscom memory regions overlap because the size is wrong. The P10 core+L2 xscom region size is allocated as 0x1000 (with some unused ranges). "EC" is used as a closer match, as "EX" includes L3 which has a disjoint xscom range that would require a different region if it were implemented. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org> Message-ID: <20230706053923.115003-2-npiggin@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
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3 changed files with 6 additions and 3 deletions
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@ -46,6 +46,7 @@ struct PnvCoreClass {
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DeviceClass parent_class;
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const MemoryRegionOps *xscom_ops;
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uint64_t xscom_size;
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};
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#define PNV_CORE_TYPE_SUFFIX "-" TYPE_PNV_CORE
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@ -133,7 +133,7 @@ struct PnvXScomInterfaceClass {
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#define PNV10_XSCOM_EC_BASE(core) \
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((uint64_t) PNV10_XSCOM_EQ_BASE(core) | PNV10_XSCOM_EC(core & 0x3))
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#define PNV10_XSCOM_EC_SIZE 0x100000
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#define PNV10_XSCOM_EC_SIZE 0x1000
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#define PNV10_XSCOM_PSIHB_BASE 0x3011D00
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#define PNV10_XSCOM_PSIHB_SIZE 0x100
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