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target/ppc: implement vrlq

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Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220225210936.1749575-26-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
This commit is contained in:
Matheus Ferst 2022-03-02 06:51:37 +01:00 • committed by Cédric Le Goater
parent 02c74f0efc
commit aa0f34ec3f
2 changed files with 49 additions and 0 deletions
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1
target/ppc/insn32.decode
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@ -491,6 +491,7 @@ VRLB 000100 ..... ..... ..... 00000000100 @VX
VRLH 000100 ..... ..... ..... 00001000100 @VX VRLH 000100 ..... ..... ..... 00001000100 @VX
VRLW 000100 ..... ..... ..... 00010000100 @VX VRLW 000100 ..... ..... ..... 00010000100 @VX
VRLD 000100 ..... ..... ..... 00011000100 @VX VRLD 000100 ..... ..... ..... 00011000100 @VX
VRLQ 000100 ..... ..... ..... 00000000101 @VX
VRLWMI 000100 ..... ..... ..... 00010000101 @VX VRLWMI 000100 ..... ..... ..... 00010000101 @VX
VRLDMI 000100 ..... ..... ..... 00011000101 @VX VRLDMI 000100 ..... ..... ..... 00011000101 @VX

48
target/ppc/translate/vmx-impl.c.inc
View file

@ -1055,6 +1055,54 @@ TRANS_FLAGS2(ISA310, VSLQ, do_vector_shift_quad, false, false);
TRANS_FLAGS2(ISA310, VSRQ, do_vector_shift_quad, true, false); TRANS_FLAGS2(ISA310, VSRQ, do_vector_shift_quad, true, false);
TRANS_FLAGS2(ISA310, VSRAQ, do_vector_shift_quad, true, true); TRANS_FLAGS2(ISA310, VSRAQ, do_vector_shift_quad, true, true);
static bool trans_VRLQ(DisasContext *ctx, arg_VX *a)
{
TCGv_i64 ah, al, n, t0, t1, zero = tcg_constant_i64(0);
REQUIRE_VECTOR(ctx);
REQUIRE_INSNS_FLAGS2(ctx, ISA310);
ah = tcg_temp_new_i64();
al = tcg_temp_new_i64();
n = tcg_temp_new_i64();
t0 = tcg_temp_new_i64();
t1 = tcg_temp_new_i64();
get_avr64(ah, a->vra, true);
get_avr64(al, a->vra, false);
get_avr64(n, a->vrb, true);
tcg_gen_mov_i64(t0, ah);
tcg_gen_andi_i64(t1, n, 64);
tcg_gen_movcond_i64(TCG_COND_NE, ah, t1, zero, al, ah);
tcg_gen_movcond_i64(TCG_COND_NE, al, t1, zero, t0, al);
tcg_gen_andi_i64(n, n, 0x3F);
tcg_gen_shl_i64(t0, ah, n);
tcg_gen_shl_i64(t1, al, n);
tcg_gen_xori_i64(n, n, 63);
tcg_gen_shr_i64(al, al, n);
tcg_gen_shri_i64(al, al, 1);
tcg_gen_or_i64(t0, al, t0);
tcg_gen_shr_i64(ah, ah, n);
tcg_gen_shri_i64(ah, ah, 1);
tcg_gen_or_i64(t1, ah, t1);
set_avr64(a->vrt, t0, true);
set_avr64(a->vrt, t1, false);
tcg_temp_free_i64(ah);
tcg_temp_free_i64(al);
tcg_temp_free_i64(n);
tcg_temp_free_i64(t0);
tcg_temp_free_i64(t1);
return true;
}
#define GEN_VXFORM_SAT(NAME, VECE, NORM, SAT, OPC2, OPC3) \ #define GEN_VXFORM_SAT(NAME, VECE, NORM, SAT, OPC2, OPC3) \
static void glue(glue(gen_, NAME), _vec)(unsigned vece, TCGv_vec t, \ static void glue(glue(gen_, NAME), _vec)(unsigned vece, TCGv_vec t, \
TCGv_vec sat, TCGv_vec a, \ TCGv_vec sat, TCGv_vec a, \