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hw/arm/smmu: Split smmuv3_translate()
smmuv3_translate() does everything from STE/CD parsing to TLB lookup and PTW. Soon, when nesting is supported, stage-1 data (tt, CD) needs to be translated using stage-2. Split smmuv3_translate() to 3 functions: - smmu_translate(): in smmu-common.c, which does the TLB lookup, PTW, TLB insertion, all the functions are already there, this just puts them together. This also simplifies the code as it consolidates event generation in case of TLB lookup permission failure or in TT selection. - smmuv3_do_translate(): in smmuv3.c, Calls smmu_translate() and does the event population in case of errors. - smmuv3_translate(), now calls smmuv3_do_translate() for translation while the rest is the same. Also, add stage in trace_smmuv3_translate_success() Reviewed-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Mostafa Saleh <smostafa@google.com> Reviewed-by: Jean-Philippe Brucker <jean-philippe@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20240715084519.1189624-6-smostafa@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Mostafa Saleh
Peter Maydell
parent
f6cc198050
commit
a9e3f4c1eb
4 changed files with 142 additions and 121 deletions
194
hw/arm/smmuv3.c
194
hw/arm/smmuv3.c
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@ -827,6 +827,76 @@ static void smmuv3_flush_config(SMMUDevice *sdev)
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g_hash_table_remove(bc->configs, sdev);
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}
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/* Do translation with TLB lookup. */
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static SMMUTranslationStatus smmuv3_do_translate(SMMUv3State *s, hwaddr addr,
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SMMUTransCfg *cfg,
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SMMUEventInfo *event,
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IOMMUAccessFlags flag,
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SMMUTLBEntry **out_entry)
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{
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SMMUPTWEventInfo ptw_info = {};
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SMMUState *bs = ARM_SMMU(s);
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SMMUTLBEntry *cached_entry = NULL;
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cached_entry = smmu_translate(bs, cfg, addr, flag, &ptw_info);
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if (!cached_entry) {
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/* All faults from PTW has S2 field. */
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event->u.f_walk_eabt.s2 = (ptw_info.stage == SMMU_STAGE_2);
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switch (ptw_info.type) {
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case SMMU_PTW_ERR_WALK_EABT:
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event->type = SMMU_EVT_F_WALK_EABT;
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event->u.f_walk_eabt.addr = addr;
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event->u.f_walk_eabt.rnw = flag & 0x1;
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event->u.f_walk_eabt.class = (ptw_info.stage == SMMU_STAGE_2) ?
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SMMU_CLASS_IN : SMMU_CLASS_TT;
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event->u.f_walk_eabt.addr2 = ptw_info.addr;
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break;
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case SMMU_PTW_ERR_TRANSLATION:
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if (PTW_RECORD_FAULT(cfg)) {
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event->type = SMMU_EVT_F_TRANSLATION;
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event->u.f_translation.addr = addr;
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event->u.f_translation.addr2 = ptw_info.addr;
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event->u.f_translation.class = SMMU_CLASS_IN;
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event->u.f_translation.rnw = flag & 0x1;
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}
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break;
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case SMMU_PTW_ERR_ADDR_SIZE:
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if (PTW_RECORD_FAULT(cfg)) {
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event->type = SMMU_EVT_F_ADDR_SIZE;
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event->u.f_addr_size.addr = addr;
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event->u.f_addr_size.addr2 = ptw_info.addr;
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event->u.f_addr_size.class = SMMU_CLASS_IN;
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event->u.f_addr_size.rnw = flag & 0x1;
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}
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break;
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case SMMU_PTW_ERR_ACCESS:
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if (PTW_RECORD_FAULT(cfg)) {
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event->type = SMMU_EVT_F_ACCESS;
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event->u.f_access.addr = addr;
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event->u.f_access.addr2 = ptw_info.addr;
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event->u.f_access.class = SMMU_CLASS_IN;
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event->u.f_access.rnw = flag & 0x1;
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}
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break;
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case SMMU_PTW_ERR_PERMISSION:
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if (PTW_RECORD_FAULT(cfg)) {
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event->type = SMMU_EVT_F_PERMISSION;
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event->u.f_permission.addr = addr;
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event->u.f_permission.addr2 = ptw_info.addr;
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event->u.f_permission.class = SMMU_CLASS_IN;
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event->u.f_permission.rnw = flag & 0x1;
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}
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break;
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default:
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g_assert_not_reached();
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}
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return SMMU_TRANS_ERROR;
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}
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*out_entry = cached_entry;
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return SMMU_TRANS_SUCCESS;
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}
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/* Entry point to SMMU, does everything. */
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static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,
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IOMMUAccessFlags flag, int iommu_idx)
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{
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@ -836,12 +906,7 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,
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SMMUEventInfo event = {.type = SMMU_EVT_NONE,
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.sid = sid,
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.inval_ste_allowed = false};
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SMMUPTWEventInfo ptw_info = {};
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SMMUTranslationStatus status;
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SMMUState *bs = ARM_SMMU(s);
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uint64_t page_mask, aligned_addr;
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SMMUTLBEntry *cached_entry = NULL;
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SMMUTransTableInfo *tt;
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SMMUTransCfg *cfg = NULL;
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IOMMUTLBEntry entry = {
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.target_as = &address_space_memory,
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@ -850,11 +915,7 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,
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.addr_mask = ~(hwaddr)0,
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.perm = IOMMU_NONE,
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};
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/*
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* Combined attributes used for TLB lookup, as only one stage is supported,
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* it will hold attributes based on the enabled stage.
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*/
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SMMUTransTableInfo tt_combined;
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SMMUTLBEntry *cached_entry = NULL;
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qemu_mutex_lock(&s->mutex);
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@ -883,115 +944,7 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,
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goto epilogue;
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}
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if (cfg->stage == SMMU_STAGE_1) {
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/* Select stage1 translation table. */
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tt = select_tt(cfg, addr);
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if (!tt) {
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if (cfg->record_faults) {
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event.type = SMMU_EVT_F_TRANSLATION;
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event.u.f_translation.addr = addr;
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event.u.f_translation.rnw = flag & 0x1;
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}
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status = SMMU_TRANS_ERROR;
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goto epilogue;
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}
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tt_combined.granule_sz = tt->granule_sz;
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tt_combined.tsz = tt->tsz;
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} else {
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/* Stage2. */
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tt_combined.granule_sz = cfg->s2cfg.granule_sz;
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tt_combined.tsz = cfg->s2cfg.tsz;
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}
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/*
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* TLB lookup looks for granule and input size for a translation stage,
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* as only one stage is supported right now, choose the right values
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* from the configuration.
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*/
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page_mask = (1ULL << tt_combined.granule_sz) - 1;
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aligned_addr = addr & ~page_mask;
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cached_entry = smmu_iotlb_lookup(bs, cfg, &tt_combined, aligned_addr);
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if (cached_entry) {
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if ((flag & IOMMU_WO) && !(cached_entry->entry.perm & IOMMU_WO)) {
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status = SMMU_TRANS_ERROR;
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/*
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* We know that the TLB only contains either stage-1 or stage-2 as
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* nesting is not supported. So it is sufficient to check the
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* translation stage to know the TLB stage for now.
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*/
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event.u.f_walk_eabt.s2 = (cfg->stage == SMMU_STAGE_2);
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if (PTW_RECORD_FAULT(cfg)) {
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event.type = SMMU_EVT_F_PERMISSION;
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event.u.f_permission.addr = addr;
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event.u.f_permission.rnw = flag & 0x1;
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}
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} else {
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status = SMMU_TRANS_SUCCESS;
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}
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goto epilogue;
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}
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cached_entry = g_new0(SMMUTLBEntry, 1);
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if (smmu_ptw(cfg, aligned_addr, flag, cached_entry, &ptw_info)) {
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/* All faults from PTW has S2 field. */
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event.u.f_walk_eabt.s2 = (ptw_info.stage == SMMU_STAGE_2);
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g_free(cached_entry);
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switch (ptw_info.type) {
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case SMMU_PTW_ERR_WALK_EABT:
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event.type = SMMU_EVT_F_WALK_EABT;
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event.u.f_walk_eabt.addr = addr;
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event.u.f_walk_eabt.rnw = flag & 0x1;
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/* Stage-2 (only) is class IN while stage-1 is class TT */
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event.u.f_walk_eabt.class = (ptw_info.stage == SMMU_STAGE_2) ?
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SMMU_CLASS_IN : SMMU_CLASS_TT;
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event.u.f_walk_eabt.addr2 = ptw_info.addr;
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break;
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case SMMU_PTW_ERR_TRANSLATION:
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if (PTW_RECORD_FAULT(cfg)) {
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event.type = SMMU_EVT_F_TRANSLATION;
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event.u.f_translation.addr = addr;
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event.u.f_translation.addr2 = ptw_info.addr;
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event.u.f_translation.class = SMMU_CLASS_IN;
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event.u.f_translation.rnw = flag & 0x1;
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}
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break;
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case SMMU_PTW_ERR_ADDR_SIZE:
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if (PTW_RECORD_FAULT(cfg)) {
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event.type = SMMU_EVT_F_ADDR_SIZE;
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event.u.f_addr_size.addr = addr;
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event.u.f_addr_size.addr2 = ptw_info.addr;
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event.u.f_translation.class = SMMU_CLASS_IN;
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event.u.f_addr_size.rnw = flag & 0x1;
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}
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break;
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case SMMU_PTW_ERR_ACCESS:
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if (PTW_RECORD_FAULT(cfg)) {
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event.type = SMMU_EVT_F_ACCESS;
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event.u.f_access.addr = addr;
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event.u.f_access.addr2 = ptw_info.addr;
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event.u.f_translation.class = SMMU_CLASS_IN;
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event.u.f_access.rnw = flag & 0x1;
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}
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break;
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case SMMU_PTW_ERR_PERMISSION:
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if (PTW_RECORD_FAULT(cfg)) {
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event.type = SMMU_EVT_F_PERMISSION;
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event.u.f_permission.addr = addr;
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event.u.f_permission.addr2 = ptw_info.addr;
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event.u.f_translation.class = SMMU_CLASS_IN;
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event.u.f_permission.rnw = flag & 0x1;
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}
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break;
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default:
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g_assert_not_reached();
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}
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status = SMMU_TRANS_ERROR;
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} else {
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smmu_iotlb_insert(bs, cfg, cached_entry);
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status = SMMU_TRANS_SUCCESS;
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}
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status = smmuv3_do_translate(s, addr, cfg, &event, flag, &cached_entry);
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epilogue:
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qemu_mutex_unlock(&s->mutex);
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@ -1002,7 +955,8 @@ epilogue:
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(addr & cached_entry->entry.addr_mask);
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entry.addr_mask = cached_entry->entry.addr_mask;
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trace_smmuv3_translate_success(mr->parent_obj.name, sid, addr,
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entry.translated_addr, entry.perm);
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entry.translated_addr, entry.perm,
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cfg->stage);
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break;
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case SMMU_TRANS_DISABLE:
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entry.perm = flag;
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