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arm_gic: Add GICC_APRn state to the GICState

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The GICC_APRn registers are not currently supported by the ARM GIC v2.0
emulation.  This patch adds the missing state.

Note that we also change the number of APRs to use a define GIC_NR_APRS
based on the maximum number of preemption levels.  This patch also adds
RAZ/WI accessors for the four registers on the emulated CPU interface.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Christoffer Dall 2013-11-18 19:26:33 -08:00 • committed by Peter Maydell
parent a1b1d277cd
commit a9d477c4e3
3 changed files with 27 additions and 2 deletions
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19
include/hw/intc/arm_gic_common.h
View file

@ -31,6 +31,9 @@
/* Maximum number of possible CPU interfaces, determined by GIC architecture */
#define GIC_NCPU 8
#define MAX_NR_GROUP_PRIO 128
#define GIC_NR_APRS (MAX_NR_GROUP_PRIO / 32)
typedef struct gic_irq_state {
/* The enable bits are only banked for per-cpu interrupts. */
uint8_t enabled;
@ -75,6 +78,22 @@ typedef struct GICState {
uint8_t bpr[GIC_NCPU];
uint8_t abpr[GIC_NCPU];
/* The APR is implementation defined, so we choose a layout identical to
* the KVM ABI layout for QEMU's implementation of the gic:
* If an interrupt for preemption level X is active, then
* APRn[X mod 32] == 0b1, where n = X / 32
* otherwise the bit is clear.
*
* TODO: rewrite the interrupt acknowlege/complete routines to use
* the APR registers to track the necessary information to update
* s->running_priority[] on interrupt completion (ie completely remove
* last_active[][] and running_irq[]). This will be necessary if we ever
* want to support TCG<->KVM migration, or TCG guests which can
* do power management involving powering down and restarting
* the GIC.
*/
uint32_t apr[GIC_NR_APRS][GIC_NCPU];
uint32_t num_cpu;
MemoryRegion iomem; /* Distributor */