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target/arm: Convert exception generation instructions to decodetree

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Convert the exception generation instructions SVC, HVC, SMC, BRK and
HLT to decodetree.

The old decoder decoded the halting-debug insnns DCPS1, DCPS2 and
DCPS3 just in order to then make them UNDEF; as with DRPS, we don't
bother to decode them, but document the patterns in a64.decode.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230602155223.2040685-8-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2023-06-19 11:20:21 +01:00
parent 6e3c8049ad
commit a97d3c18f6
2 changed files with 79 additions and 109 deletions
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15
target/arm/tcg/a64.decode
View file

@ -215,3 +215,18 @@ MSR_i_SVCR 1101 0101 0000 0 011 0100 0 mask:2 imm:1 011 11111
SYS 1101 0101 00 l:1 01 op1:3 crn:4 crm:4 op2:3 rt:5 op0=1 SYS 1101 0101 00 l:1 01 op1:3 crn:4 crm:4 op2:3 rt:5 op0=1
SYS 1101 0101 00 l:1 10 op1:3 crn:4 crm:4 op2:3 rt:5 op0=2 SYS 1101 0101 00 l:1 10 op1:3 crn:4 crm:4 op2:3 rt:5 op0=2
SYS 1101 0101 00 l:1 11 op1:3 crn:4 crm:4 op2:3 rt:5 op0=3 SYS 1101 0101 00 l:1 11 op1:3 crn:4 crm:4 op2:3 rt:5 op0=3
# Exception generation
@i16 .... .... ... imm:16 ... .. &i
SVC 1101 0100 000 ................ 000 01 @i16
HVC 1101 0100 000 ................ 000 10 @i16
SMC 1101 0100 000 ................ 000 11 @i16
BRK 1101 0100 001 ................ 000 00 @i16
HLT 1101 0100 010 ................ 000 00 @i16
# These insns always UNDEF unless in halting debug state, which
# we don't implement. So we don't need to decode them. The patterns
# are listed here as documentation.
# DCPS1 1101 0100 101 ................ 000 01 @i16
# DCPS2 1101 0100 101 ................ 000 10 @i16
# DCPS3 1101 0100 101 ................ 000 11 @i16

123
target/arm/tcg/translate-a64.c
View file

@ -2313,119 +2313,77 @@ static bool trans_SYS(DisasContext *s, arg_SYS *a)
return true; return true;
} }
/* Exception generation static bool trans_SVC(DisasContext *s, arg_i *a)
*
* 31 24 23 21 20 5 4 2 1 0
* +-----------------+-----+------------------------+-----+----+
* | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
* +-----------------------+------------------------+----------+
*/
static void disas_exc(DisasContext *s, uint32_t insn)
{ {
int opc = extract32(insn, 21, 3); /*
int op2_ll = extract32(insn, 0, 5); * For SVC, HVC and SMC we advance the single-step state
int imm16 = extract32(insn, 5, 16);
uint32_t syndrome;
switch (opc) {
case 0:
/* For SVC, HVC and SMC we advance the single-step state
* machine before taking the exception. This is architecturally * machine before taking the exception. This is architecturally
* mandated, to ensure that single-stepping a system call * mandated, to ensure that single-stepping a system call
* instruction works properly. * instruction works properly.
*/ */
switch (op2_ll) { uint32_t syndrome = syn_aa64_svc(a->imm);
case 1: /* SVC */
syndrome = syn_aa64_svc(imm16);
if (s->fgt_svc) { if (s->fgt_svc) {
gen_exception_insn_el(s, 0, EXCP_UDEF, syndrome, 2); gen_exception_insn_el(s, 0, EXCP_UDEF, syndrome, 2);
break; return true;
} }
gen_ss_advance(s); gen_ss_advance(s);
gen_exception_insn(s, 4, EXCP_SWI, syndrome); gen_exception_insn(s, 4, EXCP_SWI, syndrome);
break; return true;
case 2: /* HVC */ }
static bool trans_HVC(DisasContext *s, arg_i *a)
{
if (s->current_el == 0) { if (s->current_el == 0) {
unallocated_encoding(s); unallocated_encoding(s);
break; return true;
} }
/* The pre HVC helper handles cases when HVC gets trapped /*
* The pre HVC helper handles cases when HVC gets trapped
* as an undefined insn by runtime configuration. * as an undefined insn by runtime configuration.
*/ */
gen_a64_update_pc(s, 0); gen_a64_update_pc(s, 0);
gen_helper_pre_hvc(cpu_env); gen_helper_pre_hvc(cpu_env);
/* Architecture requires ss advance before we do the actual work */
gen_ss_advance(s); gen_ss_advance(s);
gen_exception_insn_el(s, 4, EXCP_HVC, syn_aa64_hvc(imm16), 2); gen_exception_insn_el(s, 4, EXCP_HVC, syn_aa64_hvc(a->imm), 2);
break; return true;
case 3: /* SMC */ }
static bool trans_SMC(DisasContext *s, arg_i *a)
{
if (s->current_el == 0) { if (s->current_el == 0) {
unallocated_encoding(s); unallocated_encoding(s);
break; return true;
} }
gen_a64_update_pc(s, 0); gen_a64_update_pc(s, 0);
gen_helper_pre_smc(cpu_env, tcg_constant_i32(syn_aa64_smc(imm16))); gen_helper_pre_smc(cpu_env, tcg_constant_i32(syn_aa64_smc(a->imm)));
/* Architecture requires ss advance before we do the actual work */
gen_ss_advance(s); gen_ss_advance(s);
gen_exception_insn_el(s, 4, EXCP_SMC, syn_aa64_smc(imm16), 3); gen_exception_insn_el(s, 4, EXCP_SMC, syn_aa64_smc(a->imm), 3);
break; return true;
default: }
unallocated_encoding(s);
break; static bool trans_BRK(DisasContext *s, arg_i *a)
} {
break; gen_exception_bkpt_insn(s, syn_aa64_bkpt(a->imm));
case 1: return true;
if (op2_ll != 0) { }
unallocated_encoding(s);
break; static bool trans_HLT(DisasContext *s, arg_i *a)
} {
/* BRK */ /*
gen_exception_bkpt_insn(s, syn_aa64_bkpt(imm16)); * HLT. This has two purposes.
break;
case 2:
if (op2_ll != 0) {
unallocated_encoding(s);
break;
}
/* HLT. This has two purposes.
* Architecturally, it is an external halting debug instruction. * Architecturally, it is an external halting debug instruction.
* Since QEMU doesn't implement external debug, we treat this as * Since QEMU doesn't implement external debug, we treat this as
* it is required for halting debug disabled: it will UNDEF. * it is required for halting debug disabled: it will UNDEF.
* Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction. * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction.
*/ */
if (semihosting_enabled(s->current_el == 0) && imm16 == 0xf000) { if (semihosting_enabled(s->current_el == 0) && a->imm == 0xf000) {
gen_exception_internal_insn(s, EXCP_SEMIHOST); gen_exception_internal_insn(s, EXCP_SEMIHOST);
} else { } else {
unallocated_encoding(s); unallocated_encoding(s);
} }
break; return true;
case 5:
if (op2_ll < 1 || op2_ll > 3) {
unallocated_encoding(s);
break;
}
/* DCPS1, DCPS2, DCPS3 */
unallocated_encoding(s);
break;
default:
unallocated_encoding(s);
break;
}
}
/* Branches, exception generating and system instructions */
static void disas_b_exc_sys(DisasContext *s, uint32_t insn)
{
switch (extract32(insn, 25, 7)) {
case 0x6a: /* Exception generation / System */
if (insn & (1 << 24)) {
unallocated_encoding(s);
} else {
disas_exc(s, insn);
}
break;
default:
unallocated_encoding(s);
break;
}
} }
/* /*
@ -14188,9 +14146,6 @@ static bool btype_destination_ok(uint32_t insn, bool bt, int btype)
static void disas_a64_legacy(DisasContext *s, uint32_t insn) static void disas_a64_legacy(DisasContext *s, uint32_t insn)
{ {
switch (extract32(insn, 25, 4)) { switch (extract32(insn, 25, 4)) {
case 0xa: case 0xb: /* Branch, exception generation and system insns */
disas_b_exc_sys(s, insn);
break;
case 0x4: case 0x4:
case 0x6: case 0x6:
case 0xc: case 0xc: