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Implement power state changes (IDLE and SLEEP) for PXA.

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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2762 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
balrog 2007-05-01 01:28:01 +00:00
parent 4207117c93
commit a90b7318ba
4 changed files with 26 additions and 14 deletions
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23
cpu-exec.c
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@ -279,9 +279,10 @@ int cpu_exec(CPUState *env1)
#elif defined(TARGET_ARM)
if (env1->halted) {
/* An interrupt wakes the CPU even if the I and F CPSR bits are
set. */
if (env1->interrupt_request
& (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD)) {
set. We use EXITTB to silently wake CPU without causing an
actual interrupt. */
if (env1->interrupt_request &
(CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB)) {
env1->halted = 0;
} else {
return EXCP_HALTED;
@ -432,6 +433,15 @@ int cpu_exec(CPUState *env1)
env->exception_index = EXCP_DEBUG;
cpu_loop_exit();
}
#if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \
defined(TARGET_PPC) || defined(TARGET_ALPHA)
if (interrupt_request & CPU_INTERRUPT_HALT) {
env->interrupt_request &= ~CPU_INTERRUPT_HALT;
env->halted = 1;
env->exception_index = EXCP_HLT;
cpu_loop_exit();
}
#endif
#if defined(TARGET_I386)
if ((interrupt_request & CPU_INTERRUPT_SMI) &&
!(env->hflags & HF_SMM_MASK)) {
@ -514,12 +524,7 @@ int cpu_exec(CPUState *env1)
} else if (interrupt_request & CPU_INTERRUPT_TIMER) {
//do_interrupt(0, 0, 0, 0, 0);
env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
} else if (interrupt_request & CPU_INTERRUPT_HALT) {
env->interrupt_request &= ~CPU_INTERRUPT_HALT;
env->halted = 1;
env->exception_index = EXCP_HLT;
cpu_loop_exit();
}
}
#elif defined(TARGET_ARM)
if (interrupt_request & CPU_INTERRUPT_FIQ
&& !(env->uncached_cpsr & CPSR_F)) {