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aspeed queue:
* Removal of the swift-bmc machine * New Secure Boot Controller model * Improvements on the rainier machine * Various small cleanups -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmIbOjkACgkQUaNDx8/7 7KHl4w//QySSZtdkk0fLIHg6q4aSeehLZWro5JVRs+ZGtmM6ixi95RNQwEyiM3g6 fHbkgsE3YHh3rnX5KckTPwMq+LctLSebrUtOvHQyTcHckCjwn90Vyaw7hSBROeGz 8Yieb6qda2kEnX61yGlE80go3WDuA2kyRw2bvHOhT5Vzsb2Xq8xflziFv+gHH4NT Hf/AiCSh6uCILT0JyhZF4Swzip+jDGytryPdBThBtptShyscCgIKb9GqVTVHbWXi dCe+eDDPUm7npOfP5RmHE249tz+SwS+YejTShewt0FALzglxu/GZI3UNEg0Ays+0 E7uWeSFrgQE5lZvht3Z7Duc0GCGQxYkVwhUtr2e/9dLUIRTrcdj/55h/VgeaSzR5 3RXtbwNAaumE0JdgKXFwmBuPNRNzZa89hrBcvswkcVXtlB2hsWlWLniKJHbafNHk vOMABrEeWCZYT794J0yFrunCUFPCNUXpPYJJdRBeIktiHzRGJYHraX7i/aJ5ltse VaDVbEdHaB11H8Y2cQJtjda/zM84DaqGQj9EkQPCRe7w3bnWQLSJ1qcahszV0P+Z y+DkoFRr3LKVE9dIS/N4gwIBWk5AymqSqAVizQ61rq8ZetUNdgTT12EC39djhATi OfudYiQKc33gvYOLLFSST2tiv/NK/GfIGc2Ag1qME30NYnam50Q= =0F2M -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/legoater/tags/pull-aspeed-20220227' into staging aspeed queue: * Removal of the swift-bmc machine * New Secure Boot Controller model * Improvements on the rainier machine * Various small cleanups # gpg: Signature made Sun 27 Feb 2022 08:45:45 GMT # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * remotes/legoater/tags/pull-aspeed-20220227: aspeed/sdmc: Add trace events aspeed/smc: Add an address mask on segment registers aspeed: Introduce a create_pca9552() helper aspeed: rainier: Add strap values taken from hardware aspeed: rainier: Add i2c LED devices ast2600: Add Secure Boot Controller model arm: Remove swift-bmc machine Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
a8d39f5b5a
13 changed files with 236 additions and 79 deletions
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@ -106,17 +106,6 @@ struct AspeedMachineState {
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SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
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SCU_AST2500_HW_STRAP_RESERVED1)
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/* Swift hardware value: 0xF11AD206 */
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#define SWIFT_BMC_HW_STRAP1 ( \
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AST2500_HW_STRAP1_DEFAULTS | \
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SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
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SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
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SCU_AST2500_HW_STRAP_UART_DEBUG | \
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SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
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SCU_H_PLL_BYPASS_EN | \
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SCU_AST2500_HW_STRAP_ACPI_ENABLE | \
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SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
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#define G220A_BMC_HW_STRAP1 ( \
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SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
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SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
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@ -171,8 +160,8 @@ struct AspeedMachineState {
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#define TACOMA_BMC_HW_STRAP2 0x00000040
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/* Rainier hardware value: (QEMU prototype) */
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#define RAINIER_BMC_HW_STRAP1 0x00000000
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#define RAINIER_BMC_HW_STRAP2 0x00000000
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#define RAINIER_BMC_HW_STRAP1 0x00422016
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#define RAINIER_BMC_HW_STRAP2 0x80000848
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/* Fuji hardware value */
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#define FUJI_BMC_HW_STRAP1 0x00000000
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@ -544,33 +533,10 @@ static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
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i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
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}
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static void swift_bmc_i2c_init(AspeedMachineState *bmc)
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static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr)
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{
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AspeedSoCState *soc = &bmc->soc;
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i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "pca9552", 0x60);
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/* The swift board expects a TMP275 but a TMP105 is compatible */
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i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "tmp105", 0x48);
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/* The swift board expects a pca9551 but a pca9552 is compatible */
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i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x60);
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/* The swift board expects an Epson RX8900 RTC but a ds1338 is compatible */
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i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "ds1338", 0x32);
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i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x60);
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i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c);
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/* The swift board expects a pca9539 but a pca9552 is compatible */
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i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "pca9552", 0x74);
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i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c);
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/* The swift board expects a pca9539 but a pca9552 is compatible */
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i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "pca9552",
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0x74);
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/* The swift board expects a TMP275 but a TMP105 is compatible */
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i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), "tmp105", 0x48);
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i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), "tmp105", 0x4a);
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i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id),
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TYPE_PCA9552, addr);
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}
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static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
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@ -589,9 +555,9 @@ static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
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smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54,
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eeprom4_54);
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/* PCA9539 @ 0x76, but PCA9552 is compatible */
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i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "pca9552", 0x76);
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create_pca9552(soc, 4, 0x76);
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/* PCA9539 @ 0x77, but PCA9552 is compatible */
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i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "pca9552", 0x77);
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create_pca9552(soc, 4, 0x77);
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/* bus 6 : */
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i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48);
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@ -602,8 +568,8 @@ static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
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uint8_t *eeprom8_56 = g_malloc0(8 * 1024);
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smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56,
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eeprom8_56);
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i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x60);
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i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x61);
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create_pca9552(soc, 8, 0x60);
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create_pca9552(soc, 8, 0x61);
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/* bus 8 : adc128d818 @ 0x1d */
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/* bus 8 : adc128d818 @ 0x1f */
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@ -741,8 +707,7 @@ static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc)
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i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ds1338", 0x68);
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/* It expects a pca9555 but a pca9552 is compatible */
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i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_PCA9552,
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0x20);
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create_pca9552(soc, 8, 0x30);
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}
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static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
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@ -752,6 +717,8 @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
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aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB);
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create_pca9552(soc, 3, 0x61);
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/* The rainier expects a TMP275 but a TMP105 is compatible */
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i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
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0x48);
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@ -764,11 +731,14 @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
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aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
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aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
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aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB);
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create_pca9552(soc, 4, 0x60);
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i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
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0x48);
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i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
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0x49);
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create_pca9552(soc, 5, 0x60);
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create_pca9552(soc, 5, 0x61);
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i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5),
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"pca9546", 0x70);
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aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
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@ -787,8 +757,13 @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
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aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB);
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aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB);
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create_pca9552(soc, 7, 0x30);
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create_pca9552(soc, 7, 0x31);
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create_pca9552(soc, 7, 0x32);
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create_pca9552(soc, 7, 0x33);
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/* Bus 7: TODO max31785@52 */
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i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x61);
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create_pca9552(soc, 7, 0x60);
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create_pca9552(soc, 7, 0x61);
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i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x76);
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/* Bus 7: TODO si7021-a20@20 */
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i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105,
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@ -802,7 +777,8 @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
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0x4a);
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aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, 64 * KiB);
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aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 64 * KiB);
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i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x61);
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create_pca9552(soc, 8, 0x60);
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create_pca9552(soc, 8, 0x61);
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/* Bus 8: ucd90320@11 */
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/* Bus 8: ucd90320@b */
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/* Bus 8: ucd90320@c */
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@ -823,13 +799,17 @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
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"pca9546", 0x70);
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aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
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aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
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create_pca9552(soc, 11, 0x60);
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aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB);
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create_pca9552(soc, 13, 0x60);
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aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB);
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create_pca9552(soc, 14, 0x60);
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aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB);
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create_pca9552(soc, 15, 0x60);
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}
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static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr,
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@ -1102,26 +1082,6 @@ static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data)
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aspeed_soc_num_cpus(amc->soc_name);
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};
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static void aspeed_machine_swift_class_init(ObjectClass *oc, void *data)
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{
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MachineClass *mc = MACHINE_CLASS(oc);
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AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
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mc->desc = "OpenPOWER Swift BMC (ARM1176)";
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amc->soc_name = "ast2500-a1";
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amc->hw_strap1 = SWIFT_BMC_HW_STRAP1;
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amc->fmc_model = "mx66l1g45g";
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amc->spi_model = "mx66l1g45g";
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amc->num_cs = 2;
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amc->i2c_init = swift_bmc_i2c_init;
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mc->default_ram_size = 512 * MiB;
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mc->default_cpus = mc->min_cpus = mc->max_cpus =
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aspeed_soc_num_cpus(amc->soc_name);
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mc->deprecation_reason = "redundant system. Please use a similar "
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"OpenPOWER BMC, Witherspoon or Romulus.";
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};
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static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data)
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{
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MachineClass *mc = MACHINE_CLASS(oc);
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@ -1277,10 +1237,6 @@ static const TypeInfo aspeed_machine_types[] = {
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.name = MACHINE_TYPE_NAME("romulus-bmc"),
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.parent = TYPE_ASPEED_MACHINE,
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.class_init = aspeed_machine_romulus_class_init,
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}, {
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.name = MACHINE_TYPE_NAME("swift-bmc"),
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.parent = TYPE_ASPEED_MACHINE,
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.class_init = aspeed_machine_swift_class_init,
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}, {
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.name = MACHINE_TYPE_NAME("sonorapass-bmc"),
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.parent = TYPE_ASPEED_MACHINE,
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@ -47,6 +47,7 @@ static const hwaddr aspeed_soc_ast2600_memmap[] = {
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[ASPEED_DEV_XDMA] = 0x1E6E7000,
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[ASPEED_DEV_ADC] = 0x1E6E9000,
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[ASPEED_DEV_DP] = 0x1E6EB000,
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[ASPEED_DEV_SBC] = 0x1E6F2000,
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[ASPEED_DEV_VIDEO] = 0x1E700000,
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[ASPEED_DEV_SDHCI] = 0x1E740000,
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[ASPEED_DEV_EMMC] = 0x1E750000,
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@ -227,6 +228,8 @@ static void aspeed_soc_ast2600_init(Object *obj)
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object_initialize_child(obj, "hace", &s->hace, typename);
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object_initialize_child(obj, "i3c", &s->i3c, TYPE_ASPEED_I3C);
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object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_SBC);
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}
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/*
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@ -539,6 +542,12 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
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/* The AST2600 I3C controller has one IRQ per bus. */
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq);
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}
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/* Secure Boot Controller */
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->sbc), errp)) {
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return;
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}
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sysbus_mmio_map(SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_SBC]);
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}
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static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
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