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pcie: Add helper to declare PASID capability for a pcie device
Signed-off-by: Clement Mathieu--Drif <clement.mathieu--drif@eviden.com> Message-Id: <20250520071823.764266-2-clement.mathieu--drif@eviden.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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3 changed files with 35 additions and 1 deletions
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@ -1214,3 +1214,28 @@ void pcie_acs_reset(PCIDevice *dev)
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pci_set_word(dev->config + dev->exp.acs_cap + PCI_ACS_CTRL, 0);
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pci_set_word(dev->config + dev->exp.acs_cap + PCI_ACS_CTRL, 0);
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}
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}
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}
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}
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/* PASID */
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void pcie_pasid_init(PCIDevice *dev, uint16_t offset, uint8_t pasid_width,
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bool exec_perm, bool priv_mod)
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{
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static const uint16_t control_reg_rw_mask = 0x07;
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uint16_t capability_reg;
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assert(pasid_width <= PCI_EXT_CAP_PASID_MAX_WIDTH);
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pcie_add_capability(dev, PCI_EXT_CAP_ID_PASID, PCI_PASID_VER, offset,
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PCI_EXT_CAP_PASID_SIZEOF);
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capability_reg = ((uint16_t)pasid_width) << PCI_PASID_CAP_WIDTH_SHIFT;
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capability_reg |= exec_perm ? PCI_PASID_CAP_EXEC : 0;
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capability_reg |= priv_mod ? PCI_PASID_CAP_PRIV : 0;
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pci_set_word(dev->config + offset + PCI_PASID_CAP, capability_reg);
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/* Everything is disabled by default */
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pci_set_word(dev->config + offset + PCI_PASID_CTRL, 0);
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pci_set_word(dev->wmask + offset + PCI_PASID_CTRL, control_reg_rw_mask);
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dev->exp.pasid_cap = offset;
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}
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@ -70,8 +70,9 @@ struct PCIExpressDevice {
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uint16_t aer_cap;
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uint16_t aer_cap;
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PCIEAERLog aer_log;
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PCIEAERLog aer_log;
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/* Offset of ATS capability in config space */
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/* Offset of ATS and PASID capabilities in config space */
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uint16_t ats_cap;
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uint16_t ats_cap;
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uint16_t pasid_cap;
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/* ACS */
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/* ACS */
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uint16_t acs_cap;
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uint16_t acs_cap;
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@ -150,4 +151,7 @@ void pcie_cap_slot_unplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
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Error **errp);
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Error **errp);
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void pcie_cap_slot_unplug_request_cb(HotplugHandler *hotplug_dev,
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void pcie_cap_slot_unplug_request_cb(HotplugHandler *hotplug_dev,
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DeviceState *dev, Error **errp);
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DeviceState *dev, Error **errp);
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void pcie_pasid_init(PCIDevice *dev, uint16_t offset, uint8_t pasid_width,
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bool exec_perm, bool priv_mod);
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#endif /* QEMU_PCIE_H */
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#endif /* QEMU_PCIE_H */
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@ -86,6 +86,11 @@ typedef enum PCIExpLinkWidth {
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#define PCI_ARI_VER 1
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#define PCI_ARI_VER 1
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#define PCI_ARI_SIZEOF 8
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#define PCI_ARI_SIZEOF 8
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/* PASID */
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#define PCI_PASID_VER 1
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#define PCI_EXT_CAP_PASID_MAX_WIDTH 20
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#define PCI_PASID_CAP_WIDTH_SHIFT 8
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/* AER */
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/* AER */
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#define PCI_ERR_VER 2
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#define PCI_ERR_VER 2
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#define PCI_ERR_SIZEOF 0x48
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#define PCI_ERR_SIZEOF 0x48
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