motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-14 21:52:18 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

pcie: Add helper to declare PASID capability for a pcie device

Browse source 
Signed-off-by: Clement Mathieu--Drif <clement.mathieu--drif@eviden.com>
Message-Id: <20250520071823.764266-2-clement.mathieu--drif@eviden.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
CLEMENT MATHIEU--DRIF 2025-05-20 07:18:51 +00:00 • committed by Michael S. Tsirkin
parent 0f178860df
commit a8d178e149
3 changed files with 35 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

25
hw/pci/pcie.c
View file

@ -1214,3 +1214,28 @@ void pcie_acs_reset(PCIDevice *dev)
pci_set_word(dev->config + dev->exp.acs_cap + PCI_ACS_CTRL, 0); pci_set_word(dev->config + dev->exp.acs_cap + PCI_ACS_CTRL, 0);
} }
} }
/* PASID */
void pcie_pasid_init(PCIDevice *dev, uint16_t offset, uint8_t pasid_width,
bool exec_perm, bool priv_mod)
{
static const uint16_t control_reg_rw_mask = 0x07;
uint16_t capability_reg;
assert(pasid_width <= PCI_EXT_CAP_PASID_MAX_WIDTH);
pcie_add_capability(dev, PCI_EXT_CAP_ID_PASID, PCI_PASID_VER, offset,
PCI_EXT_CAP_PASID_SIZEOF);
capability_reg = ((uint16_t)pasid_width) << PCI_PASID_CAP_WIDTH_SHIFT;
capability_reg |= exec_perm ? PCI_PASID_CAP_EXEC : 0;
capability_reg |= priv_mod ? PCI_PASID_CAP_PRIV : 0;
pci_set_word(dev->config + offset + PCI_PASID_CAP, capability_reg);
/* Everything is disabled by default */
pci_set_word(dev->config + offset + PCI_PASID_CTRL, 0);
pci_set_word(dev->wmask + offset + PCI_PASID_CTRL, control_reg_rw_mask);
dev->exp.pasid_cap = offset;
}

6
include/hw/pci/pcie.h
View file

@ -70,8 +70,9 @@ struct PCIExpressDevice {
uint16_t aer_cap; uint16_t aer_cap;
PCIEAERLog aer_log; PCIEAERLog aer_log;
/* Offset of ATS capability in config space */ /* Offset of ATS and PASID capabilities in config space */
uint16_t ats_cap; uint16_t ats_cap;
uint16_t pasid_cap;
/* ACS */ /* ACS */
uint16_t acs_cap; uint16_t acs_cap;
@ -150,4 +151,7 @@ void pcie_cap_slot_unplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
Error **errp); Error **errp);
void pcie_cap_slot_unplug_request_cb(HotplugHandler *hotplug_dev, void pcie_cap_slot_unplug_request_cb(HotplugHandler *hotplug_dev,
DeviceState *dev, Error **errp); DeviceState *dev, Error **errp);
void pcie_pasid_init(PCIDevice *dev, uint16_t offset, uint8_t pasid_width,
bool exec_perm, bool priv_mod);
#endif /* QEMU_PCIE_H */ #endif /* QEMU_PCIE_H */

5
include/hw/pci/pcie_regs.h
View file

@ -86,6 +86,11 @@ typedef enum PCIExpLinkWidth {
#define PCI_ARI_VER 1 #define PCI_ARI_VER 1
#define PCI_ARI_SIZEOF 8 #define PCI_ARI_SIZEOF 8
/* PASID */
#define PCI_PASID_VER 1
#define PCI_EXT_CAP_PASID_MAX_WIDTH 20
#define PCI_PASID_CAP_WIDTH_SHIFT 8
/* AER */ /* AER */
#define PCI_ERR_VER 2 #define PCI_ERR_VER 2
#define PCI_ERR_SIZEOF 0x48 #define PCI_ERR_SIZEOF 0x48