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Misc HW patches

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Merge tag 'hw-misc-20250610' of https://github.com/philmd/qemu into staging

Misc HW patches

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# gpg: Signature made Tue 10 Jun 2025 09:09:46 EDT
# gpg:                using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD  6BB2 E3E3 2C2C DEAD C0DE

* tag 'hw-misc-20250610' of https://github.com/philmd/qemu: (24 commits)
  hw/net/i82596: Factor configure function out
  hw/net/i82596: Update datasheet URL
  hw/misc/stm32_rcc: Fix stm32_rcc_write() arguments order
  hw/riscv/riscv-iommu: Remove definition of RISCVIOMMU[Pci|Sys]Class
  hw/gpio/aspeed: Fix definition of AspeedGPIOClass
  hw/virtio/virtio-pmem: Fix definition of VirtIOPMEMClass
  hw/virtio/virtio-mem: Fix definition of VirtIOMEMClass
  tests/unit/test-char: Avoid using g_alloca()
  backends/tpm: Avoid using g_alloca()
  hw/gpio/pca9552: Avoid using g_newa()
  hw/core/cpu: Move CacheType to general cpu.h
  accel/hvf: Fix TYPE_HVF_ACCEL instance size
  tests/functional: Add a test for the Arduino UNO machine
  MAINTAINERS: Update Akihiko Odaki's affiliation
  pc-bios: ensure installed ROMs don't have execute permissions
  hw/ppc/e500: Use SysBusDevice API to access TYPE_CCSR's internal resources
  hw/net/fsl_etsec: Set default MAC address
  hw/ppc/e500: Move clock and TB frequency to machine class
  hw/hyperv/balloon: Consolidate OBJECT_DEFINE_SIMPLE_TYPE_WITH_INTERFACES
  hw/core/resetcontainer: Consolidate OBJECT_DECLARE_SIMPLE_TYPE
  ...

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
Stefan Hajnoczi 2025-06-11 11:37:59 -04:00
commit a8b5c10c71
31 changed files with 166 additions and 168 deletions
Download patch file Download diff file Expand all files Collapse all files

3
.mailmap
View file

@ -67,7 +67,8 @@ Andrey Drobyshev <andrey.drobyshev@virtuozzo.com> Andrey Drobyshev via <qemu-blo
BALATON Zoltan <balaton@eik.bme.hu> BALATON Zoltan via <qemu-ppc@nongnu.org>
# Next, replace old addresses by a more recent one.
Akihiko Odaki <akihiko.odaki@daynix.com> <akihiko.odaki@gmail.com>
Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp> <akihiko.odaki@daynix.com>
Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp> <akihiko.odaki@gmail.com>
Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> <aleksandar.markovic@mips.com>
Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> <aleksandar.markovic@imgtec.com>
Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> <amarkovic@wavecomp.com>

19
MAINTAINERS
View file

@ -219,7 +219,7 @@ S: Maintained
F: docs/system/target-avr.rst
F: gdb-xml/avr-cpu.xml
F: target/avr/
F: tests/functional/test_avr_mega2560.py
F: tests/functional/test_avr_*.py
Hexagon TCG CPUs
M: Brian Cain <brian.cain@oss.qualcomm.com>
@ -1236,6 +1236,7 @@ Arduino
M: Philippe Mathieu-Daudé <philmd@linaro.org>
S: Maintained
F: hw/avr/arduino.c
F: tests/functional/test_avr_uno.py
HP-PARISC Machines
------------------
@ -2519,7 +2520,7 @@ F: tests/qtest/fuzz-megasas-test.c
Network packet abstractions
M: Dmitry Fleytman <dmitry.fleytman@gmail.com>
R: Akihiko Odaki <akihiko.odaki@daynix.com>
R: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>
S: Maintained
F: include/net/eth.h
F: net/eth.c
@ -2549,13 +2550,13 @@ F: docs/specs/rocker.rst
e1000x
M: Dmitry Fleytman <dmitry.fleytman@gmail.com>
R: Akihiko Odaki <akihiko.odaki@daynix.com>
R: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>
S: Maintained
F: hw/net/e1000x*
e1000e
M: Dmitry Fleytman <dmitry.fleytman@gmail.com>
R: Akihiko Odaki <akihiko.odaki@daynix.com>
R: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>
S: Maintained
F: hw/net/e1000e*
F: tests/qtest/fuzz-e1000e-test.c
@ -2563,9 +2564,9 @@ F: tests/qtest/e1000e-test.c
F: tests/qtest/libqos/e1000e.*
igb
M: Akihiko Odaki <akihiko.odaki@daynix.com>
M: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>
R: Sriram Yagnaraman <sriram.yagnaraman@ericsson.com>
S: Maintained
S: Odd Fixes
F: docs/system/devices/igb.rst
F: hw/net/igb*
F: tests/functional/test_netdev_ethtool.py
@ -2910,7 +2911,7 @@ Core Audio framework backend
M: Gerd Hoffmann <kraxel@redhat.com>
M: Philippe Mathieu-Daudé <philmd@linaro.org>
R: Christian Schoenebeck <qemu_oss@crudebyte.com>
R: Akihiko Odaki <akihiko.odaki@daynix.com>
R: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>
S: Odd Fixes
F: audio/coreaudio.m
@ -3211,7 +3212,7 @@ F: tests/functional/test_vnc.py
Cocoa graphics
M: Peter Maydell <peter.maydell@linaro.org>
M: Philippe Mathieu-Daudé <philmd@linaro.org>
R: Akihiko Odaki <akihiko.odaki@daynix.com>
R: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>
S: Odd Fixes
F: ui/cocoa.m
@ -3738,7 +3739,7 @@ F: util/iova-tree.c
elf2dmp
M: Viktor Prutyanov <viktor.prutyanov@phystech.edu>
R: Akihiko Odaki <akihiko.odaki@daynix.com>
R: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>
S: Maintained
F: contrib/elf2dmp/

1
accel/hvf/hvf-accel-ops.c
View file

@ -366,6 +366,7 @@ static void hvf_accel_class_init(ObjectClass *oc, const void *data)
static const TypeInfo hvf_accel_type = {
.name = TYPE_HVF_ACCEL,
.parent = TYPE_ACCEL,
.instance_size = sizeof(HVFState),
.class_init = hvf_accel_class_init,
};

4
backends/tpm/tpm_emulator.c
View file

@ -129,11 +129,11 @@ static int tpm_emulator_ctrlcmd(TPMEmulator *tpm, unsigned long cmd, void *msg,
CharBackend *dev = &tpm->ctrl_chr;
uint32_t cmd_no = cpu_to_be32(cmd);
ssize_t n = sizeof(uint32_t) + msg_len_in;
uint8_t *buf = NULL;
ptm_res res;
WITH_QEMU_LOCK_GUARD(&tpm->mutex) {
buf = g_alloca(n);
g_autofree uint8_t *buf = g_malloc(n);
memcpy(buf, &cmd_no, sizeof(cmd_no));
memcpy(buf + sizeof(cmd_no), msg, msg_len_in);

24
hw/char/sh_serial.c
View file

@ -78,10 +78,6 @@ struct SHSerialState {
qemu_irq bri;
};
typedef struct {} SHSerialStateClass;
OBJECT_DEFINE_TYPE(SHSerialState, sh_serial, SH_SERIAL, SYS_BUS_DEVICE)
static void sh_serial_clear_fifo(SHSerialState *s)
{
memset(s->rx_fifo, 0, SH_RX_FIFO_LENGTH);
@ -434,17 +430,13 @@ static void sh_serial_realize(DeviceState *d, Error **errp)
s->etu = NANOSECONDS_PER_SECOND / 9600;
}
static void sh_serial_finalize(Object *obj)
static void sh_serial_unrealize(DeviceState *dev)
{
SHSerialState *s = SH_SERIAL(obj);
SHSerialState *s = SH_SERIAL(dev);
timer_del(&s->fifo_timeout_timer);
}
static void sh_serial_init(Object *obj)
{
}
static const Property sh_serial_properties[] = {
DEFINE_PROP_CHR("chardev", SHSerialState, chr),
DEFINE_PROP_UINT8("features", SHSerialState, feat, 0),
@ -456,7 +448,19 @@ static void sh_serial_class_init(ObjectClass *oc, const void *data)
device_class_set_props(dc, sh_serial_properties);
dc->realize = sh_serial_realize;
dc->unrealize = sh_serial_unrealize;
device_class_set_legacy_reset(dc, sh_serial_reset);
/* Reason: part of SuperH CPU/SoC, needs to be wired up */
dc->user_creatable = false;
}
static const TypeInfo sh_serial_types[] = {
{
.name = TYPE_SH_SERIAL,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(SHSerialState),
.class_init = sh_serial_class_init,
},
};
DEFINE_TYPES(sh_serial_types)

2
hw/gpio/pca9552.c
View file

@ -76,7 +76,7 @@ static void pca955x_display_pins_status(PCA955xState *s,
return;
}
if (trace_event_get_state_backends(TRACE_PCA955X_GPIO_STATUS)) {
char *buf = g_newa(char, k->pin_count + 1);
char buf[PCA955X_PIN_COUNT_MAX + 1];
for (i = 0; i < k->pin_count; i++) {
if (extract32(pins_status, i, 1)) {

9
hw/hyperv/hv-balloon.c
View file

@ -67,10 +67,6 @@
* these requests
*/
struct HvBalloonClass {
VMBusDeviceClass parent_class;
} HvBalloonClass;
typedef enum State {
/* not a real state */
S_NO_CHANGE = 0,
@ -162,8 +158,9 @@ typedef struct HvBalloon {
MemoryRegion *mr;
} HvBalloon;
OBJECT_DEFINE_TYPE_WITH_INTERFACES(HvBalloon, hv_balloon, HV_BALLOON, VMBUS_DEVICE, \
{ TYPE_MEMORY_DEVICE }, { })
OBJECT_DEFINE_SIMPLE_TYPE_WITH_INTERFACES(HvBalloon, hv_balloon, \
HV_BALLOON, VMBUS_DEVICE, \
{ TYPE_MEMORY_DEVICE }, { })
#define HV_BALLOON_SET_STATE(hvb, news) \
do { \

2
hw/misc/stm32_rcc.c
View file

@ -60,7 +60,7 @@ static void stm32_rcc_write(void *opaque, hwaddr addr,
uint32_t value = val64;
uint32_t prev_value, new_value, irq_offset;
trace_stm32_rcc_write(value, addr);
trace_stm32_rcc_write(addr, value);
if (addr > STM32_RCC_DCKCFGR2) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%"HWADDR_PRIx"\n",

1
hw/net/fsl_etsec/etsec.c
View file

@ -389,6 +389,7 @@ static void etsec_realize(DeviceState *dev, Error **errp)
{
eTSEC *etsec = ETSEC_COMMON(dev);
qemu_macaddr_default_if_unset(&etsec->conf.macaddr);
etsec->nic = qemu_new_nic(&net_etsec_info, &etsec->conf,
object_get_typename(OBJECT(dev)), dev->id,
&dev->mem_reentrancy_guard, etsec);

38
hw/net/i82596.c
View file

@ -5,7 +5,7 @@
* This work is licensed under the GNU GPL license version 2 or later.
*
* This software was written to be compatible with the specification:
* https://www.intel.com/assets/pdf/general/82596ca.pdf
* https://parisc.docs.kernel.org/en/latest/_downloads/96672be0650d9fc046bbcea40b92482f/82596CA.pdf
*/
#include "qemu/osdep.h"
@ -177,6 +177,26 @@ static void set_individual_address(I82596State *s, uint32_t addr)
trace_i82596_new_mac(nc->info_str);
}
static void i82596_configure(I82596State *s, uint32_t addr)
{
uint8_t byte_cnt;
byte_cnt = get_byte(addr + 8) & 0x0f;
byte_cnt = MAX(byte_cnt, 4);
byte_cnt = MIN(byte_cnt, sizeof(s->config));
/* copy byte_cnt max. */
address_space_read(&address_space_memory, addr + 8,
MEMTXATTRS_UNSPECIFIED, s->config, byte_cnt);
/* config byte according to page 35ff */
s->config[2] &= 0x82; /* mask valid bits */
s->config[2] |= 0x40;
s->config[7] &= 0xf7; /* clear zero bit */
assert(I596_NOCRC_INS == 0); /* do CRC insertion */
s->config[10] = MAX(s->config[10], 5); /* min frame length */
s->config[12] &= 0x40; /* only full duplex field valid */
s->config[13] |= 0x3f; /* set ones in byte 13 */
}
static void set_multicast_list(I82596State *s, uint32_t addr)
{
uint16_t mc_count, i;
@ -234,7 +254,6 @@ static void command_loop(I82596State *s)
{
uint16_t cmd;
uint16_t status;
uint8_t byte_cnt;
DBG(printf("STARTING COMMAND LOOP cmd_p=%08x\n", s->cmd_p));
@ -254,20 +273,7 @@ static void command_loop(I82596State *s)
set_individual_address(s, s->cmd_p);
break;
case CmdConfigure:
byte_cnt = get_byte(s->cmd_p + 8) & 0x0f;
byte_cnt = MAX(byte_cnt, 4);
byte_cnt = MIN(byte_cnt, sizeof(s->config));
/* copy byte_cnt max. */
address_space_read(&address_space_memory, s->cmd_p + 8,
MEMTXATTRS_UNSPECIFIED, s->config, byte_cnt);
/* config byte according to page 35ff */
s->config[2] &= 0x82; /* mask valid bits */
s->config[2] |= 0x40;
s->config[7] &= 0xf7; /* clear zero bit */
assert(I596_NOCRC_INS == 0); /* do CRC insertion */
s->config[10] = MAX(s->config[10], 5); /* min frame length */
s->config[12] &= 0x40; /* only full duplex field valid */
s->config[13] |= 0x3f; /* set ones in byte 13 */
i82596_configure(s, s->cmd_p);
break;
case CmdTDR:
/* get signal LINK */

8
hw/pci-host/ppce500.c
View file

@ -16,7 +16,6 @@
#include "qemu/osdep.h"
#include "hw/irq.h"
#include "hw/ppc/e500-ccsr.h"
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
#include "hw/pci/pci_device.h"
@ -418,11 +417,12 @@ static const VMStateDescription vmstate_ppce500_pci = {
static void e500_pcihost_bridge_realize(PCIDevice *d, Error **errp)
{
PPCE500PCIBridgeState *b = PPC_E500_PCI_BRIDGE(d);
PPCE500CCSRState *ccsr = CCSR(
SysBusDevice *ccsr = SYS_BUS_DEVICE(
object_resolve_path_component(qdev_get_machine(), "e500-ccsr"));
MemoryRegion *ccsr_space = sysbus_mmio_get_region(ccsr, 0);
memory_region_init_alias(&b->bar0, OBJECT(ccsr), "e500-pci-bar0", &ccsr->ccsr_space,
0, int128_get64(ccsr->ccsr_space.size));
memory_region_init_alias(&b->bar0, OBJECT(ccsr), "e500-pci-bar0",
ccsr_space, 0, int128_get64(ccsr_space->size));
pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &b->bar0);
}

85
hw/pci-host/raven.c
View file

@ -24,7 +24,6 @@
*/
#include "qemu/osdep.h"
#include "qemu/datadir.h"
#include "qemu/units.h"
#include "qemu/log.h"
#include "qapi/error.h"
@ -35,9 +34,7 @@
#include "migration/vmstate.h"
#include "hw/intc/i8259.h"
#include "hw/irq.h"
#include "hw/loader.h"
#include "hw/or-irq.h"
#include "elf.h"
#include "qom/object.h"
#define TYPE_RAVEN_PCI_DEVICE "raven"
@ -47,10 +44,6 @@ OBJECT_DECLARE_SIMPLE_TYPE(RavenPCIState, RAVEN_PCI_DEVICE)
struct RavenPCIState {
PCIDevice dev;
uint32_t elf_machine;
char *bios_name;
MemoryRegion bios;
};
typedef struct PRePPCIState PREPPCIState;
@ -75,11 +68,8 @@ struct PRePPCIState {
RavenPCIState pci_dev;
int contiguous_map;
bool is_legacy_prep;
};
#define BIOS_SIZE (1 * MiB)
#define PCI_IO_BASE_ADDR 0x80000000 /* Physical address on main bus */
static inline uint32_t raven_pci_io_config(hwaddr addr)
@ -243,22 +233,18 @@ static void raven_pcihost_realizefn(DeviceState *d, Error **errp)
MemoryRegion *address_space_mem = get_system_memory();
int i;
if (s->is_legacy_prep) {
for (i = 0; i < PCI_NUM_PINS; i++) {
sysbus_init_irq(dev, &s->pci_irqs[i]);
}
} else {
/* According to PReP specification section 6.1.6 "System Interrupt
* Assignments", all PCI interrupts are routed via IRQ 15 */
s->or_irq = OR_IRQ(object_new(TYPE_OR_IRQ));
object_property_set_int(OBJECT(s->or_irq), "num-lines", PCI_NUM_PINS,
&error_fatal);
qdev_realize(DEVICE(s->or_irq), NULL, &error_fatal);
sysbus_init_irq(dev, &s->or_irq->out_irq);
/*
* According to PReP specification section 6.1.6 "System Interrupt
* Assignments", all PCI interrupts are routed via IRQ 15
*/
s->or_irq = OR_IRQ(object_new(TYPE_OR_IRQ));
object_property_set_int(OBJECT(s->or_irq), "num-lines", PCI_NUM_PINS,
&error_fatal);
qdev_realize(DEVICE(s->or_irq), NULL, &error_fatal);
sysbus_init_irq(dev, &s->or_irq->out_irq);
for (i = 0; i < PCI_NUM_PINS; i++) {
s->pci_irqs[i] = qdev_get_gpio_in(DEVICE(s->or_irq), i);
}
for (i = 0; i < PCI_NUM_PINS; i++) {
s->pci_irqs[i] = qdev_get_gpio_in(DEVICE(s->or_irq), i);
}
qdev_init_gpio_in(d, raven_change_gpio, 1);
@ -338,48 +324,9 @@ static void raven_pcihost_initfn(Object *obj)
static void raven_realize(PCIDevice *d, Error **errp)
{
RavenPCIState *s = RAVEN_PCI_DEVICE(d);
char *filename;
int bios_size = -1;
d->config[PCI_CACHE_LINE_SIZE] = 0x08;
d->config[PCI_LATENCY_TIMER] = 0x10;
d->config[PCI_CAPABILITY_LIST] = 0x00;
if (!memory_region_init_rom_nomigrate(&s->bios, OBJECT(s), "bios",
BIOS_SIZE, errp)) {
return;
}
memory_region_add_subregion(get_system_memory(), (uint32_t)(-BIOS_SIZE),
&s->bios);
if (s->bios_name) {
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, s->bios_name);
if (filename) {
if (s->elf_machine != EM_NONE) {
bios_size = load_elf(filename, NULL, NULL, NULL, NULL,
NULL, NULL, NULL,
ELFDATA2MSB, s->elf_machine, 0, 0);
}
if (bios_size < 0) {
bios_size = get_image_size(filename);
if (bios_size > 0 && bios_size <= BIOS_SIZE) {
hwaddr bios_addr;
bios_size = (bios_size + 0xfff) & ~0xfff;
bios_addr = (uint32_t)(-BIOS_SIZE);
bios_size = load_image_targphys(filename, bios_addr,
bios_size);
}
}
}
g_free(filename);
if (bios_size < 0 || bios_size > BIOS_SIZE) {
memory_region_del_subregion(get_system_memory(), &s->bios);
error_setg(errp, "Could not load bios image '%s'", s->bios_name);
return;
}
}
vmstate_register_ram_global(&s->bios);
}
static const VMStateDescription vmstate_raven = {
@ -422,22 +369,12 @@ static const TypeInfo raven_info = {
},
};
static const Property raven_pcihost_properties[] = {
DEFINE_PROP_UINT32("elf-machine", PREPPCIState, pci_dev.elf_machine,
EM_NONE),
DEFINE_PROP_STRING("bios-name", PREPPCIState, pci_dev.bios_name),
/* Temporary workaround until legacy prep machine is removed */
DEFINE_PROP_BOOL("is-legacy-prep", PREPPCIState, is_legacy_prep,
false),
};
static void raven_pcihost_class_init(ObjectClass *klass, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
dc->realize = raven_pcihost_realizefn;
device_class_set_props(dc, raven_pcihost_properties);
dc->fw_name = "pci";
}

26
hw/ppc/e500.c
View file

@ -79,8 +79,6 @@
#define MPC85XX_ESDHC_IRQ 72
#define RTC_REGS_OFFSET 0x68
#define PLATFORM_CLK_FREQ_HZ (400 * 1000 * 1000)
struct boot_info
{
uint32_t dt_base;
@ -120,7 +118,7 @@ static uint32_t *pci_map_create(void *fdt, uint32_t mpic, int first_slot,
}
static void dt_serial_create(void *fdt, unsigned long long offset,
const char *soc, const char *mpic,
const char *soc, uint32_t freq, const char *mpic,
const char *alias, int idx, bool defcon)
{
char *ser;
@ -131,7 +129,7 @@ static void dt_serial_create(void *fdt, unsigned long long offset,
qemu_fdt_setprop_string(fdt, ser, "compatible", "ns16550");
qemu_fdt_setprop_cells(fdt, ser, "reg", offset, 0x100);
qemu_fdt_setprop_cell(fdt, ser, "cell-index", idx);
qemu_fdt_setprop_cell(fdt, ser, "clock-frequency", PLATFORM_CLK_FREQ_HZ);
qemu_fdt_setprop_cell(fdt, ser, "clock-frequency", freq);
qemu_fdt_setprop_cells(fdt, ser, "interrupts", 42, 2);
qemu_fdt_setprop_phandle(fdt, ser, "interrupt-parent", mpic);
qemu_fdt_setprop_string(fdt, "/aliases", alias, ser);
@ -382,8 +380,7 @@ static int ppce500_load_device_tree(PPCE500MachineState *pms,
int fdt_size;
void *fdt;
uint8_t hypercall[16];
uint32_t clock_freq = PLATFORM_CLK_FREQ_HZ;
uint32_t tb_freq = PLATFORM_CLK_FREQ_HZ;
uint32_t clock_freq, tb_freq;
int i;
char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus";
char *soc;
@ -484,6 +481,9 @@ static int ppce500_load_device_tree(PPCE500MachineState *pms,
if (kvmppc_get_hasidle(env)) {
qemu_fdt_setprop(fdt, "/hypervisor", "has-idle", NULL, 0);
}
} else {
clock_freq = pmc->clock_freq;
tb_freq = pmc->tb_freq;
}
/* Create CPU nodes */
@ -564,12 +564,12 @@ static int ppce500_load_device_tree(PPCE500MachineState *pms,
*/
if (serial_hd(1)) {
dt_serial_create(fdt, MPC8544_SERIAL1_REGS_OFFSET,
soc, mpic, "serial1", 1, false);
soc, pmc->clock_freq, mpic, "serial1", 1, false);
}
if (serial_hd(0)) {
dt_serial_create(fdt, MPC8544_SERIAL0_REGS_OFFSET,
soc, mpic, "serial0", 0, true);
soc, pmc->clock_freq, mpic, "serial0", 0, true);
}
/* i2c */
@ -931,7 +931,6 @@ void ppce500_init(MachineState *machine)
CPUPPCState *firstenv = NULL;
MemoryRegion *ccsr_addr_space;
SysBusDevice *s;
PPCE500CCSRState *ccsr;
I2CBus *i2c;
irqs = g_new0(IrqLines, smp_cpus);
@ -968,7 +967,7 @@ void ppce500_init(MachineState *machine)
env->spr_cb[SPR_BOOKE_PIR].default_value = cs->cpu_index = i;
env->mpic_iack = pmc->ccsrbar_base + MPC8544_MPIC_REGS_OFFSET + 0xa0;
ppc_booke_timers_init(cpu, PLATFORM_CLK_FREQ_HZ, PPC_TIMER_E500);
ppc_booke_timers_init(cpu, pmc->tb_freq, PPC_TIMER_E500);
/* Register reset handler */
if (!i) {
@ -993,10 +992,10 @@ void ppce500_init(MachineState *machine)
memory_region_add_subregion(address_space_mem, 0, machine->ram);
dev = qdev_new("e500-ccsr");
s = SYS_BUS_DEVICE(dev);
object_property_add_child(OBJECT(machine), "e500-ccsr", OBJECT(dev));
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
ccsr = CCSR(dev);
ccsr_addr_space = &ccsr->ccsr_space;
sysbus_realize_and_unref(s, &error_fatal);
ccsr_addr_space = sysbus_mmio_get_region(s, 0);
memory_region_add_subregion(address_space_mem, pmc->ccsrbar_base,
ccsr_addr_space);
@ -1284,6 +1283,7 @@ static void e500_ccsr_initfn(Object *obj)
PPCE500CCSRState *ccsr = CCSR(obj);
memory_region_init(&ccsr->ccsr_space, obj, "e500-ccsr",
MPC8544_CCSRBAR_SIZE);
sysbus_init_mmio(SYS_BUS_DEVICE(ccsr), &ccsr->ccsr_space);
}
static const TypeInfo e500_ccsr_info = {

4
hw/ppc/e500.h
View file

@ -5,6 +5,8 @@
#include "hw/platform-bus.h"
#include "qom/object.h"
#define PLATFORM_CLK_FREQ_HZ (400 * 1000 * 1000)
struct PPCE500MachineState {
/*< private >*/
MachineState parent_obj;
@ -37,6 +39,8 @@ struct PPCE500MachineClass {
hwaddr pci_mmio_base;
hwaddr pci_mmio_bus_base;
hwaddr spin_base;
uint32_t clock_freq;
uint32_t tb_freq;
};
void ppce500_init(MachineState *machine);

2
hw/ppc/e500plat.c
View file

@ -93,6 +93,8 @@ static void e500plat_machine_class_init(ObjectClass *oc, const void *data)
pmc->pci_mmio_base = 0xC00000000ULL;
pmc->pci_mmio_bus_base = 0xE0000000ULL;
pmc->spin_base = 0xFEF000000ULL;
pmc->clock_freq = PLATFORM_CLK_FREQ_HZ;
pmc->tb_freq = PLATFORM_CLK_FREQ_HZ;
mc->desc = "generic paravirt e500 platform";
mc->init = e500plat_init;

2
hw/ppc/mpc8544ds.c
View file

@ -55,6 +55,8 @@ static void mpc8544ds_machine_class_init(ObjectClass *oc, const void *data)
pmc->pci_mmio_bus_base = 0xC0000000ULL;
pmc->pci_pio_base = 0xE1000000ULL;
pmc->spin_base = 0xEF000000ULL;
pmc->clock_freq = PLATFORM_CLK_FREQ_HZ;
pmc->tb_freq = PLATFORM_CLK_FREQ_HZ;
mc->desc = "mpc8544ds";
mc->init = mpc8544ds_init;

27
hw/ppc/prep.c
View file

@ -35,6 +35,7 @@
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "qemu/log.h"
#include "qemu/datadir.h"
#include "hw/loader.h"
#include "hw/rtc/mc146818rtc.h"
#include "hw/isa/pc87312.h"
@ -55,6 +56,8 @@
#define KERNEL_LOAD_ADDR 0x01000000
#define INITRD_LOAD_ADDR 0x01800000
#define BIOS_ADDR 0xfff00000
#define BIOS_SIZE (1 * MiB)
#define NVRAM_SIZE 0x2000
static void fw_cfg_boot_set(void *opaque, const char *boot_device,
@ -241,6 +244,9 @@ static void ibm_40p_init(MachineState *machine)
ISADevice *isa_dev;
ISABus *isa_bus;
void *fw_cfg;
MemoryRegion *bios = g_new(MemoryRegion, 1);
char *filename;
ssize_t bios_size = -1;
uint32_t kernel_base = 0, initrd_base = 0;
long kernel_size = 0, initrd_size = 0;
char boot_device;
@ -263,10 +269,27 @@ static void ibm_40p_init(MachineState *machine)
cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
qemu_register_reset(ppc_prep_reset, cpu);
/* allocate and load firmware */
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
if (!filename) {
error_report("Could not find bios image '%s'", bios_name);
exit(1);
}
memory_region_init_rom(bios, NULL, "bios", BIOS_SIZE, &error_fatal);
memory_region_add_subregion(get_system_memory(), BIOS_ADDR, bios);
bios_size = load_elf(filename, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
ELFDATA2MSB, PPC_ELF_MACHINE, 0, 0);
if (bios_size < 0) {
bios_size = load_image_targphys(filename, BIOS_ADDR, BIOS_SIZE);
}
if (bios_size < 0 || bios_size > BIOS_SIZE) {
error_report("Could not load bios image '%s'", filename);
return;
}
g_free(filename);
/* PCI host */
dev = qdev_new("raven-pcihost");
qdev_prop_set_string(dev, "bios-name", bios_name);
qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE);
pcihost = SYS_BUS_DEVICE(dev);
object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev));
sysbus_realize_and_unref(pcihost, &error_fatal);

6
hw/riscv/riscv-iommu-pci.c
View file

@ -68,12 +68,6 @@ typedef struct RISCVIOMMUStatePci {
RISCVIOMMUState iommu; /* common IOMMU state */
} RISCVIOMMUStatePci;
struct RISCVIOMMUPciClass {
/*< public >*/
DeviceRealize parent_realize;
ResettablePhases parent_phases;
};
/* interrupt delivery callback */
static void riscv_iommu_pci_notify(RISCVIOMMUState *iommu, unsigned vector)
{

6
hw/riscv/riscv-iommu-sys.c
View file

@ -53,12 +53,6 @@ struct RISCVIOMMUStateSys {
uint8_t *msix_pba;
};
struct RISCVIOMMUSysClass {
/*< public >*/
DeviceRealize parent_realize;
ResettablePhases parent_phases;
};
static uint64_t msix_table_mmio_read(void *opaque, hwaddr addr,
unsigned size)
{

6
include/hw/core/cpu.h
View file

@ -1126,4 +1126,10 @@ extern const VMStateDescription vmstate_cpu_common;
#define UNASSIGNED_CPU_INDEX -1
#define UNASSIGNED_CLUSTER_INDEX -1
enum CacheType {
DATA_CACHE,
INSTRUCTION_CACHE,
UNIFIED_CACHE
};
#endif

2
include/hw/core/resetcontainer.h
View file

@ -20,7 +20,7 @@
#include "qom/object.h"
#define TYPE_RESETTABLE_CONTAINER "resettable-container"
OBJECT_DECLARE_TYPE(ResettableContainer, ResettableContainerClass, RESETTABLE_CONTAINER)
OBJECT_DECLARE_SIMPLE_TYPE(ResettableContainer, RESETTABLE_CONTAINER)
/**
* resettable_container_add: Add a resettable object to the container

2
include/hw/gpio/aspeed_gpio.h
View file

@ -70,7 +70,7 @@ typedef struct AspeedGPIOReg {
} AspeedGPIOReg;
struct AspeedGPIOClass {
SysBusDevice parent_obj;
SysBusDeviceClass parent_class;
const GPIOSetProperties *props;
uint32_t nr_gpio_pins;
uint32_t nr_gpio_sets;

6
include/hw/riscv/iommu.h
View file

@ -30,14 +30,12 @@ typedef struct RISCVIOMMUState RISCVIOMMUState;
typedef struct RISCVIOMMUSpace RISCVIOMMUSpace;
#define TYPE_RISCV_IOMMU_PCI "riscv-iommu-pci"
OBJECT_DECLARE_TYPE(RISCVIOMMUStatePci, RISCVIOMMUPciClass, RISCV_IOMMU_PCI)
OBJECT_DECLARE_SIMPLE_TYPE(RISCVIOMMUStatePci, RISCV_IOMMU_PCI)
typedef struct RISCVIOMMUStatePci RISCVIOMMUStatePci;
typedef struct RISCVIOMMUPciClass RISCVIOMMUPciClass;
#define TYPE_RISCV_IOMMU_SYS "riscv-iommu-device"
OBJECT_DECLARE_TYPE(RISCVIOMMUStateSys, RISCVIOMMUSysClass, RISCV_IOMMU_SYS)
OBJECT_DECLARE_SIMPLE_TYPE(RISCVIOMMUStateSys, RISCV_IOMMU_SYS)
typedef struct RISCVIOMMUStateSys RISCVIOMMUStateSys;
typedef struct RISCVIOMMUSysClass RISCVIOMMUSysClass;
#define FDT_IRQ_TYPE_EDGE_LOW 1

2
include/hw/virtio/virtio-mem.h
View file

@ -134,7 +134,7 @@ struct VirtioMemSystemReset {
struct VirtIOMEMClass {
/* private */
VirtIODevice parent;
VirtioDeviceClass parent_class;
/* public */
void (*fill_device_info)(const VirtIOMEM *vmen, VirtioMEMDeviceInfo *vi);

2
include/hw/virtio/virtio-pmem.h
View file

@ -36,7 +36,7 @@ struct VirtIOPMEM {
struct VirtIOPMEMClass {
/* private */
VirtIODevice parent;
VirtioDeviceClass parent_class;
/* public */
void (*fill_device_info)(const VirtIOPMEM *pmem, VirtioPMEMDeviceInfo *vi);

1
include/system/hvf_int.h
View file

@ -44,6 +44,7 @@ typedef struct hvf_vcpu_caps {
struct HVFState {
AccelState parent;
hvf_slot slots[32];
int num_slots;

2
pc-bios/meson.build
View file

@ -88,7 +88,7 @@ blobs = [
]
if get_option('install_blobs')
install_data(blobs, install_dir: qemu_datadir)
install_data(blobs, install_dir: qemu_datadir, install_mode: 'rw-r--r--')
endif
subdir('descriptors')

6
target/i386/cpu.h
View file

@ -1773,12 +1773,6 @@ typedef enum TPRAccess {
/* Cache information data structures: */
enum CacheType {
DATA_CACHE,
INSTRUCTION_CACHE,
UNIFIED_CACHE
};
typedef struct CPUCacheInfo {
enum CacheType type;
uint8_t level;

1
tests/functional/meson.build
View file

@ -150,6 +150,7 @@ tests_arm_linuxuser_thorough = [
tests_avr_system_thorough = [
'avr_mega2560',
'avr_uno',
]
tests_hppa_system_quick = [

32
tests/functional/test_avr_uno.py Executable file
View file

@ -0,0 +1,32 @@
#!/usr/bin/env python3
#
# QEMU AVR Arduino UNO functional test
#
# SPDX-License-Identifier: GPL-2.0-or-later
from qemu_test import QemuSystemTest, Asset, wait_for_console_pattern
class UnoMachine(QemuSystemTest):
ASSET_UNO = Asset(
('https://github.com/RahulRNandan/LED_Blink_AVR/raw/'
'c6d602cbb974a193/build/main.elf'),
'3009a4e2cf5c5b65142f538abdf66d4dc6bc6beab7e552fff9ae314583761b72')
def test_uno(self):
"""
The binary constantly prints out 'LED Blink'
"""
self.set_machine('arduino-uno')
rom_path = self.ASSET_UNO.fetch()
self.vm.add_args('-bios', rom_path)
self.vm.set_console()
self.vm.launch()
wait_for_console_pattern(self, 'LED Blink')
if __name__ == '__main__':
QemuSystemTest.main()

3
tests/unit/test-char.c
View file

@ -993,7 +993,7 @@ static void char_udp_test_internal(Chardev *reuse_chr, int sock)
struct sockaddr_in other;
SocketIdleData d = { 0, };
Chardev *chr;
CharBackend *be;
CharBackend stack_be, *be = &stack_be;
socklen_t alen = sizeof(other);
int ret;
char buf[10];
@ -1009,7 +1009,6 @@ static void char_udp_test_internal(Chardev *reuse_chr, int sock)
chr = qemu_chr_new("client", tmp, NULL);
g_assert_nonnull(chr);
be = g_alloca(sizeof(CharBackend));
qemu_chr_fe_init(be, chr, &error_abort);
}