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RISC-V: Implement existential predicates for CSRs

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CSR predicate functions are added to the CSR table.
mstatus.FS and counter enable checks are moved
to predicate functions and two new predicates are
added to check misa.S for s* CSRs and a new PMP
CPU feature for pmp* CSRs.

Processors that don't implement S-mode will trap
on access to s* CSRs and processors that don't
implement PMP will trap on accesses to pmp* CSRs.

PMP checks are disabled in riscv_cpu_handle_mmu_fault
when the PMP CPU feature is not present.

Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
This commit is contained in:
Michael Clark 2019-01-04 23:24:14 +00:00 • committed by Palmer Dabbelt
parent 71877e2969
commit a88365c199
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GPG key ID: EF4CA1502CCBAB41
4 changed files with 105 additions and 79 deletions
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6
target/riscv/cpu.h
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@ -83,9 +83,10 @@
/* S extension denotes that Supervisor mode exists, however it is possible
to have a core that support S mode but does not have an MMU and there
is currently no bit in misa to indicate whether an MMU exists or not
so a cpu features bitfield is required */
so a cpu features bitfield is required, likewise for optional PMP support */
enum {
RISCV_FEATURE_MMU
RISCV_FEATURE_MMU,
RISCV_FEATURE_PMP
};
#define USER_VERSION_2_02_0 0x00020200
@ -314,6 +315,7 @@ typedef int (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
target_ulong *ret_value, target_ulong new_value, target_ulong write_mask);
typedef struct {
riscv_csr_predicate_fn predicate;
riscv_csr_read_fn read;
riscv_csr_write_fn write;
riscv_csr_op_fn op;