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riscv: Pass RISCVHartArrayState by pointer

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We were accidently passing RISCVHartArrayState by value instead of
pointer. The type is 824 bytes long so let's correct that and pass it by
pointer instead.

Fixes: Coverity CID 1438099
Fixes: Coverity CID 1438100
Fixes: Coverity CID 1438101
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Message-id: f3e04424723e0e222769991896cc82308fd23f76.1610751609.git.alistair.francis@wdc.com
This commit is contained in:
Alistair Francis 2021-01-15 15:00:27 -08:00
parent 138ca49a82
commit a8259b5323
5 changed files with 20 additions and 22 deletions
Download patch file Download diff file Expand all files Collapse all files

10
hw/riscv/boot.c
View file

@ -33,14 +33,12 @@
#include <libfdt.h>
bool riscv_is_32bit(RISCVHartArrayState harts)
bool riscv_is_32bit(RISCVHartArrayState *harts)
{
RISCVCPU hart = harts.harts[0];
return riscv_cpu_is_32bit(&hart.env);
return riscv_cpu_is_32bit(&harts->harts[0].env);
}
target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState harts,
target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts,
target_ulong firmware_end_addr) {
if (riscv_is_32bit(harts)) {
return QEMU_ALIGN_UP(firmware_end_addr, 4 * MiB);
@ -247,7 +245,7 @@ void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base,
&address_space_memory);
}
void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState harts,
void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts,
hwaddr start_addr,
hwaddr rom_base, hwaddr rom_size,
uint64_t kernel_entry,