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https://github.com/Motorhead1991/qemu.git
synced 2025-08-03 15:53:54 -06:00
Rename target_phys_addr_t to hwaddr
target_phys_addr_t is unwieldly, violates the C standard (_t suffixes are
reserved) and its purpose doesn't match the name (most target_phys_addr_t
addresses are not target specific). Replace it with a finger-friendly,
standards conformant hwaddr.
Outstanding patchsets can be fixed up with the command
git rebase -i --exec 'find -name "*.[ch]"
| xargs s/target_phys_addr_t/hwaddr/g' origin
Signed-off-by: Avi Kivity <avi@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Avi Kivity
Anthony Liguori
parent
50d2b4d93f
commit
a8170e5e97
383 changed files with 2240 additions and 2240 deletions
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@ -215,7 +215,7 @@ static inline int pte_check(mmu_ctx_t *ctx, int is_64b, target_ulong pte0,
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pp = pte1 & 0x00000003;
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}
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if (ptem == ctx->ptem) {
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if (ctx->raddr != (target_phys_addr_t)-1ULL) {
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if (ctx->raddr != (hwaddr)-1ULL) {
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/* all matches should have equal RPN, WIMG & PP */
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if ((ctx->raddr & mmask) != (pte1 & mmask)) {
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qemu_log("Bad RPN/WIMG/PP\n");
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@ -556,8 +556,8 @@ static inline int get_bat(CPUPPCState *env, mmu_ctx_t *ctx,
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return ret;
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}
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static inline target_phys_addr_t get_pteg_offset(CPUPPCState *env,
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target_phys_addr_t hash,
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static inline hwaddr get_pteg_offset(CPUPPCState *env,
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hwaddr hash,
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int pte_size)
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{
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return (hash * pte_size * 8) & env->htab_mask;
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@ -567,7 +567,7 @@ static inline target_phys_addr_t get_pteg_offset(CPUPPCState *env,
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static inline int find_pte2(CPUPPCState *env, mmu_ctx_t *ctx, int is_64b, int h,
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int rw, int type, int target_page_bits)
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{
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target_phys_addr_t pteg_off;
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hwaddr pteg_off;
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target_ulong pte0, pte1;
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int i, good = -1;
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int ret, r;
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@ -817,7 +817,7 @@ static int ppc_load_slb_vsid(CPUPPCState *env, target_ulong rb,
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static inline int get_segment(CPUPPCState *env, mmu_ctx_t *ctx,
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target_ulong eaddr, int rw, int type)
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{
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target_phys_addr_t hash;
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hwaddr hash;
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target_ulong vsid;
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int ds, pr, target_page_bits;
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int ret, ret2;
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@ -896,7 +896,7 @@ static inline int get_segment(CPUPPCState *env, mmu_ctx_t *ctx,
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ctx->hash[1] = ~hash;
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/* Initialize real address with an invalid value */
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ctx->raddr = (target_phys_addr_t)-1ULL;
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ctx->raddr = (hwaddr)-1ULL;
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if (unlikely(env->mmu_model == POWERPC_MMU_SOFT_6xx ||
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env->mmu_model == POWERPC_MMU_SOFT_74xx)) {
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/* Software TLB search */
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@ -926,7 +926,7 @@ static inline int get_segment(CPUPPCState *env, mmu_ctx_t *ctx,
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}
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#if defined(DUMP_PAGE_TABLES)
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if (qemu_log_enabled()) {
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target_phys_addr_t curaddr;
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hwaddr curaddr;
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uint32_t a0, a1, a2, a3;
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qemu_log("Page table: " TARGET_FMT_plx " len " TARGET_FMT_plx
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@ -1009,7 +1009,7 @@ static inline int get_segment(CPUPPCState *env, mmu_ctx_t *ctx,
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/* Generic TLB check function for embedded PowerPC implementations */
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static int ppcemb_tlb_check(CPUPPCState *env, ppcemb_tlb_t *tlb,
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target_phys_addr_t *raddrp,
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hwaddr *raddrp,
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target_ulong address, uint32_t pid, int ext,
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int i)
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{
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@ -1045,7 +1045,7 @@ static int ppcemb_tlb_search(CPUPPCState *env, target_ulong address,
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uint32_t pid)
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{
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ppcemb_tlb_t *tlb;
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target_phys_addr_t raddr;
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hwaddr raddr;
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int i, ret;
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/* Default return value is no match */
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@ -1079,7 +1079,7 @@ static inline void ppc4xx_tlb_invalidate_virt(CPUPPCState *env,
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{
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#if !defined(FLUSH_ALL_TLBS)
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ppcemb_tlb_t *tlb;
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target_phys_addr_t raddr;
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hwaddr raddr;
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target_ulong page, end;
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int i;
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@ -1104,11 +1104,11 @@ static int mmu40x_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
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int access_type)
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{
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ppcemb_tlb_t *tlb;
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target_phys_addr_t raddr;
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hwaddr raddr;
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int i, ret, zsel, zpr, pr;
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ret = -1;
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raddr = (target_phys_addr_t)-1ULL;
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raddr = (hwaddr)-1ULL;
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pr = msr_pr;
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for (i = 0; i < env->nb_tlb; i++) {
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tlb = &env->tlb.tlbe[i];
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@ -1175,7 +1175,7 @@ void store_40x_sler(CPUPPCState *env, uint32_t val)
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}
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static inline int mmubooke_check_tlb(CPUPPCState *env, ppcemb_tlb_t *tlb,
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target_phys_addr_t *raddr, int *prot,
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hwaddr *raddr, int *prot,
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target_ulong address, int rw,
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int access_type, int i)
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{
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@ -1249,11 +1249,11 @@ static int mmubooke_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
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int access_type)
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{
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ppcemb_tlb_t *tlb;
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target_phys_addr_t raddr;
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hwaddr raddr;
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int i, ret;
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ret = -1;
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raddr = (target_phys_addr_t)-1ULL;
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raddr = (hwaddr)-1ULL;
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for (i = 0; i < env->nb_tlb; i++) {
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tlb = &env->tlb.tlbe[i];
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ret = mmubooke_check_tlb(env, tlb, &raddr, &ctx->prot, address, rw,
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@ -1297,7 +1297,7 @@ void booke206_flush_tlb(CPUPPCState *env, int flags, const int check_iprot)
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tlb_flush(env, 1);
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}
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target_phys_addr_t booke206_tlb_to_page_size(CPUPPCState *env,
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hwaddr booke206_tlb_to_page_size(CPUPPCState *env,
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ppcmas_tlb_t *tlb)
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{
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int tlbm_size;
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@ -1309,7 +1309,7 @@ target_phys_addr_t booke206_tlb_to_page_size(CPUPPCState *env,
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/* TLB check function for MAS based SoftTLBs */
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int ppcmas_tlb_check(CPUPPCState *env, ppcmas_tlb_t *tlb,
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target_phys_addr_t *raddrp,
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hwaddr *raddrp,
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target_ulong address, uint32_t pid)
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{
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target_ulong mask;
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@ -1345,7 +1345,7 @@ int ppcmas_tlb_check(CPUPPCState *env, ppcmas_tlb_t *tlb,
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}
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static int mmubooke206_check_tlb(CPUPPCState *env, ppcmas_tlb_t *tlb,
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target_phys_addr_t *raddr, int *prot,
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hwaddr *raddr, int *prot,
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target_ulong address, int rw,
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int access_type)
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{
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@ -1435,11 +1435,11 @@ static int mmubooke206_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
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int access_type)
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{
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ppcmas_tlb_t *tlb;
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target_phys_addr_t raddr;
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hwaddr raddr;
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int i, j, ret;
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ret = -1;
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raddr = (target_phys_addr_t)-1ULL;
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raddr = (hwaddr)-1ULL;
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for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
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int ways = booke206_tlb_ways(env, i);
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@ -1496,7 +1496,7 @@ static void mmubooke_dump_mmu(FILE *f, fprintf_function cpu_fprintf,
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entry = &env->tlb.tlbe[0];
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for (i = 0; i < env->nb_tlb; i++, entry++) {
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target_phys_addr_t ea, pa;
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hwaddr ea, pa;
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target_ulong mask;
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uint64_t size = (uint64_t)entry->size;
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char size_buf[20];
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@ -1509,9 +1509,9 @@ static void mmubooke_dump_mmu(FILE *f, fprintf_function cpu_fprintf,
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mask = ~(entry->size - 1);
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ea = entry->EPN & mask;
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pa = entry->RPN & mask;
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#if (TARGET_PHYS_ADDR_BITS >= 36)
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#if (TARGET_PHYS_ADDR_SPACE_BITS >= 36)
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/* Extend the physical address to 36 bits */
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pa |= (target_phys_addr_t)(entry->RPN & 0xF) << 32;
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pa |= (hwaddr)(entry->RPN & 0xF) << 32;
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#endif
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size /= 1024;
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if (size >= 1024) {
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@ -1539,7 +1539,7 @@ static void mmubooke206_dump_one_tlb(FILE *f, fprintf_function cpu_fprintf,
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entry = &env->tlb.tlbm[offset];
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for (i = 0; i < tlbsize; i++, entry++) {
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target_phys_addr_t ea, pa, size;
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hwaddr ea, pa, size;
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int tsize;
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if (!(entry->mas1 & MAS1_VALID)) {
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@ -1785,7 +1785,7 @@ int get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, target_ulong eaddr,
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return ret;
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}
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target_phys_addr_t cpu_get_phys_page_debug(CPUPPCState *env, target_ulong addr)
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hwaddr cpu_get_phys_page_debug(CPUPPCState *env, target_ulong addr)
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{
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mmu_ctx_t ctx;
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@ -3145,7 +3145,7 @@ void helper_booke206_tlbsx(CPUPPCState *env, target_ulong address)
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{
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ppcmas_tlb_t *tlb = NULL;
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int i, j;
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target_phys_addr_t raddr;
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hwaddr raddr;
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uint32_t spid, sas;
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spid = (env->spr[SPR_BOOKE_MAS6] & MAS6_SPID_MASK) >> MAS6_SPID_SHIFT;
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