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https://github.com/Motorhead1991/qemu.git
synced 2025-08-03 07:43:54 -06:00
Rename target_phys_addr_t to hwaddr
target_phys_addr_t is unwieldly, violates the C standard (_t suffixes are reserved) and its purpose doesn't match the name (most target_phys_addr_t addresses are not target specific). Replace it with a finger-friendly, standards conformant hwaddr. Outstanding patchsets can be fixed up with the command git rebase -i --exec 'find -name "*.[ch]" | xargs s/target_phys_addr_t/hwaddr/g' origin Signed-off-by: Avi Kivity <avi@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
parent
50d2b4d93f
commit
a8170e5e97
383 changed files with 2240 additions and 2240 deletions
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@ -503,7 +503,7 @@ static const char *state2str(uint32_t state)
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return nr2str(ehci_state_names, ARRAY_SIZE(ehci_state_names), state);
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}
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static const char *addr2str(target_phys_addr_t addr)
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static const char *addr2str(hwaddr addr)
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{
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return nr2str(ehci_mmio_names, ARRAY_SIZE(ehci_mmio_names),
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addr + OPREGBASE);
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@ -663,7 +663,7 @@ static int ehci_get_fetch_addr(EHCIState *s, int async)
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return async ? s->a_fetch_addr : s->p_fetch_addr;
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}
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static void ehci_trace_qh(EHCIQueue *q, target_phys_addr_t addr, EHCIqh *qh)
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static void ehci_trace_qh(EHCIQueue *q, hwaddr addr, EHCIqh *qh)
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{
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/* need three here due to argument count limits */
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trace_usb_ehci_qh_ptrs(q, addr, qh->next,
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@ -681,7 +681,7 @@ static void ehci_trace_qh(EHCIQueue *q, target_phys_addr_t addr, EHCIqh *qh)
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(bool)(qh->epchar & QH_EPCHAR_I));
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}
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static void ehci_trace_qtd(EHCIQueue *q, target_phys_addr_t addr, EHCIqtd *qtd)
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static void ehci_trace_qtd(EHCIQueue *q, hwaddr addr, EHCIqtd *qtd)
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{
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/* need three here due to argument count limits */
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trace_usb_ehci_qtd_ptrs(q, addr, qtd->next, qtd->altnext);
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@ -698,7 +698,7 @@ static void ehci_trace_qtd(EHCIQueue *q, target_phys_addr_t addr, EHCIqtd *qtd)
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(bool)(qtd->token & QTD_TOKEN_XACTERR));
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}
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static void ehci_trace_itd(EHCIState *s, target_phys_addr_t addr, EHCIitd *itd)
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static void ehci_trace_itd(EHCIState *s, hwaddr addr, EHCIitd *itd)
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{
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trace_usb_ehci_itd(addr, itd->next,
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get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT),
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@ -707,7 +707,7 @@ static void ehci_trace_itd(EHCIState *s, target_phys_addr_t addr, EHCIitd *itd)
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get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR));
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}
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static void ehci_trace_sitd(EHCIState *s, target_phys_addr_t addr,
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static void ehci_trace_sitd(EHCIState *s, hwaddr addr,
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EHCIsitd *sitd)
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{
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trace_usb_ehci_sitd(addr, sitd->next,
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@ -1100,14 +1100,14 @@ static void ehci_reset(void *opaque)
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qemu_bh_cancel(s->async_bh);
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}
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static uint64_t ehci_caps_read(void *ptr, target_phys_addr_t addr,
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static uint64_t ehci_caps_read(void *ptr, hwaddr addr,
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unsigned size)
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{
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EHCIState *s = ptr;
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return s->caps[addr];
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}
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static uint64_t ehci_opreg_read(void *ptr, target_phys_addr_t addr,
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static uint64_t ehci_opreg_read(void *ptr, hwaddr addr,
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unsigned size)
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{
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EHCIState *s = ptr;
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@ -1118,7 +1118,7 @@ static uint64_t ehci_opreg_read(void *ptr, target_phys_addr_t addr,
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return val;
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}
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static uint64_t ehci_port_read(void *ptr, target_phys_addr_t addr,
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static uint64_t ehci_port_read(void *ptr, hwaddr addr,
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unsigned size)
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{
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EHCIState *s = ptr;
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@ -1157,7 +1157,7 @@ static void handle_port_owner_write(EHCIState *s, int port, uint32_t owner)
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}
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}
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static void ehci_port_write(void *ptr, target_phys_addr_t addr,
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static void ehci_port_write(void *ptr, hwaddr addr,
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uint64_t val, unsigned size)
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{
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EHCIState *s = ptr;
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@ -1202,7 +1202,7 @@ static void ehci_port_write(void *ptr, target_phys_addr_t addr,
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trace_usb_ehci_portsc_change(addr + PORTSC_BEGIN, addr >> 2, *portsc, old);
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}
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static void ehci_opreg_write(void *ptr, target_phys_addr_t addr,
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static void ehci_opreg_write(void *ptr, hwaddr addr,
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uint64_t val, unsigned size)
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{
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EHCIState *s = ptr;
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@ -1236,7 +1236,7 @@ static void musb_ep_writeh(void *opaque, int ep, int addr, uint16_t value)
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}
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/* Generic control */
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static uint32_t musb_readb(void *opaque, target_phys_addr_t addr)
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static uint32_t musb_readb(void *opaque, hwaddr addr)
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{
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MUSBState *s = (MUSBState *) opaque;
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int ep, i;
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@ -1298,7 +1298,7 @@ static uint32_t musb_readb(void *opaque, target_phys_addr_t addr)
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};
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}
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static void musb_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
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static void musb_writeb(void *opaque, hwaddr addr, uint32_t value)
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{
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MUSBState *s = (MUSBState *) opaque;
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int ep;
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@ -1385,7 +1385,7 @@ static void musb_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
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};
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}
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static uint32_t musb_readh(void *opaque, target_phys_addr_t addr)
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static uint32_t musb_readh(void *opaque, hwaddr addr)
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{
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MUSBState *s = (MUSBState *) opaque;
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int ep, i;
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@ -1439,7 +1439,7 @@ static uint32_t musb_readh(void *opaque, target_phys_addr_t addr)
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};
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}
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static void musb_writeh(void *opaque, target_phys_addr_t addr, uint32_t value)
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static void musb_writeh(void *opaque, hwaddr addr, uint32_t value)
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{
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MUSBState *s = (MUSBState *) opaque;
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int ep;
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@ -1495,7 +1495,7 @@ static void musb_writeh(void *opaque, target_phys_addr_t addr, uint32_t value)
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};
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}
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static uint32_t musb_readw(void *opaque, target_phys_addr_t addr)
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static uint32_t musb_readw(void *opaque, hwaddr addr)
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{
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MUSBState *s = (MUSBState *) opaque;
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int ep;
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@ -1513,7 +1513,7 @@ static uint32_t musb_readw(void *opaque, target_phys_addr_t addr)
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};
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}
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static void musb_writew(void *opaque, target_phys_addr_t addr, uint32_t value)
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static void musb_writew(void *opaque, hwaddr addr, uint32_t value)
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{
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MUSBState *s = (MUSBState *) opaque;
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int ep;
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@ -1473,7 +1473,7 @@ static void ohci_port_set_status(OHCIState *ohci, int portnum, uint32_t val)
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}
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static uint64_t ohci_mem_read(void *opaque,
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target_phys_addr_t addr,
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hwaddr addr,
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unsigned size)
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{
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OHCIState *ohci = opaque;
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@ -1596,7 +1596,7 @@ static uint64_t ohci_mem_read(void *opaque,
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}
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static void ohci_mem_write(void *opaque,
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target_phys_addr_t addr,
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hwaddr addr,
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uint64_t val,
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unsigned size)
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{
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@ -2364,7 +2364,7 @@ static void xhci_reset(DeviceState *dev)
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xhci_mfwrap_update(xhci);
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}
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static uint64_t xhci_cap_read(void *ptr, target_phys_addr_t reg, unsigned size)
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static uint64_t xhci_cap_read(void *ptr, hwaddr reg, unsigned size)
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{
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XHCIState *xhci = ptr;
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uint32_t ret;
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@ -2431,7 +2431,7 @@ static uint64_t xhci_cap_read(void *ptr, target_phys_addr_t reg, unsigned size)
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return ret;
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}
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static uint64_t xhci_port_read(void *ptr, target_phys_addr_t reg, unsigned size)
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static uint64_t xhci_port_read(void *ptr, hwaddr reg, unsigned size)
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{
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XHCIPort *port = ptr;
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uint32_t ret;
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@ -2455,7 +2455,7 @@ static uint64_t xhci_port_read(void *ptr, target_phys_addr_t reg, unsigned size)
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return ret;
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}
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static void xhci_port_write(void *ptr, target_phys_addr_t reg,
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static void xhci_port_write(void *ptr, hwaddr reg,
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uint64_t val, unsigned size)
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{
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XHCIPort *port = ptr;
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}
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}
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static uint64_t xhci_oper_read(void *ptr, target_phys_addr_t reg, unsigned size)
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static uint64_t xhci_oper_read(void *ptr, hwaddr reg, unsigned size)
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{
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XHCIState *xhci = ptr;
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uint32_t ret;
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return ret;
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}
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static void xhci_oper_write(void *ptr, target_phys_addr_t reg,
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static void xhci_oper_write(void *ptr, hwaddr reg,
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uint64_t val, unsigned size)
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{
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XHCIState *xhci = ptr;
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}
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}
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static uint64_t xhci_runtime_read(void *ptr, target_phys_addr_t reg,
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static uint64_t xhci_runtime_read(void *ptr, hwaddr reg,
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unsigned size)
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{
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XHCIState *xhci = ptr;
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return ret;
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}
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static void xhci_runtime_write(void *ptr, target_phys_addr_t reg,
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static void xhci_runtime_write(void *ptr, hwaddr reg,
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uint64_t val, unsigned size)
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{
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XHCIState *xhci = ptr;
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}
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}
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static uint64_t xhci_doorbell_read(void *ptr, target_phys_addr_t reg,
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static uint64_t xhci_doorbell_read(void *ptr, hwaddr reg,
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unsigned size)
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{
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/* doorbells always read as 0 */
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@ -2708,7 +2708,7 @@ static uint64_t xhci_doorbell_read(void *ptr, target_phys_addr_t reg,
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return 0;
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}
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static void xhci_doorbell_write(void *ptr, target_phys_addr_t reg,
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static void xhci_doorbell_write(void *ptr, hwaddr reg,
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uint64_t val, unsigned size)
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{
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XHCIState *xhci = ptr;
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