motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-09-09 00:07:57 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

Rename target_phys_addr_t to hwaddr

Browse source 
target_phys_addr_t is unwieldly, violates the C standard (_t suffixes are
reserved) and its purpose doesn't match the name (most target_phys_addr_t
addresses are not target specific).  Replace it with a finger-friendly,
standards conformant hwaddr.

Outstanding patchsets can be fixed up with the command

  git rebase -i --exec 'find -name "*.[ch]"
                        | xargs s/target_phys_addr_t/hwaddr/g' origin

Signed-off-by: Avi Kivity <avi@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Avi Kivity 2012-10-23 12:30:10 +02:00 • committed by Anthony Liguori
parent 50d2b4d93f
commit a8170e5e97
383 changed files with 2240 additions and 2240 deletions
Download patch file Download diff file Expand all files Collapse all files

26
hw/sun4m_iommu.c
View file

@ -130,16 +130,16 @@ typedef struct IOMMUState {
SysBusDevice busdev;
MemoryRegion iomem;
uint32_t regs[IOMMU_NREGS];
target_phys_addr_t iostart;
hwaddr iostart;
qemu_irq irq;
uint32_t version;
} IOMMUState;
static uint64_t iommu_mem_read(void *opaque, target_phys_addr_t addr,
static uint64_t iommu_mem_read(void *opaque, hwaddr addr,
unsigned size)
{
IOMMUState *s = opaque;
target_phys_addr_t saddr;
hwaddr saddr;
uint32_t ret;
saddr = addr >> 2;
@ -157,11 +157,11 @@ static uint64_t iommu_mem_read(void *opaque, target_phys_addr_t addr,
return ret;
}
static void iommu_mem_write(void *opaque, target_phys_addr_t addr,
static void iommu_mem_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
IOMMUState *s = opaque;
target_phys_addr_t saddr;
hwaddr saddr;
saddr = addr >> 2;
trace_sun4m_iommu_mem_writel(saddr, val);
@ -249,11 +249,11 @@ static const MemoryRegionOps iommu_mem_ops = {
},
};
static uint32_t iommu_page_get_flags(IOMMUState *s, target_phys_addr_t addr)
static uint32_t iommu_page_get_flags(IOMMUState *s, hwaddr addr)
{
uint32_t ret;
target_phys_addr_t iopte;
target_phys_addr_t pa = addr;
hwaddr iopte;
hwaddr pa = addr;
iopte = s->regs[IOMMU_BASE] << 4;
addr &= ~s->iostart;
@ -264,17 +264,17 @@ static uint32_t iommu_page_get_flags(IOMMUState *s, target_phys_addr_t addr)
return ret;
}
static target_phys_addr_t iommu_translate_pa(target_phys_addr_t addr,
static hwaddr iommu_translate_pa(hwaddr addr,
uint32_t pte)
{
target_phys_addr_t pa;
hwaddr pa;
pa = ((pte & IOPTE_PAGE) << 4) + (addr & ~IOMMU_PAGE_MASK);
trace_sun4m_iommu_translate_pa(addr, pa, pte);
return pa;
}
static void iommu_bad_addr(IOMMUState *s, target_phys_addr_t addr,
static void iommu_bad_addr(IOMMUState *s, hwaddr addr,
int is_write)
{
trace_sun4m_iommu_bad_addr(addr);
@ -286,12 +286,12 @@ static void iommu_bad_addr(IOMMUState *s, target_phys_addr_t addr,
qemu_irq_raise(s->irq);
}
void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
void sparc_iommu_memory_rw(void *opaque, hwaddr addr,
uint8_t *buf, int len, int is_write)
{
int l;
uint32_t flags;
target_phys_addr_t page, phys_addr;
hwaddr page, phys_addr;
while (len > 0) {
page = addr & IOMMU_PAGE_MASK;