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Rename target_phys_addr_t to hwaddr
target_phys_addr_t is unwieldly, violates the C standard (_t suffixes are reserved) and its purpose doesn't match the name (most target_phys_addr_t addresses are not target specific). Replace it with a finger-friendly, standards conformant hwaddr. Outstanding patchsets can be fixed up with the command git rebase -i --exec 'find -name "*.[ch]" | xargs s/target_phys_addr_t/hwaddr/g' origin Signed-off-by: Avi Kivity <avi@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
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50d2b4d93f
commit
a8170e5e97
383 changed files with 2240 additions and 2240 deletions
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@ -60,7 +60,7 @@ struct omap_dss_s {
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int nx;
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int ny;
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target_phys_addr_t addr[3];
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hwaddr addr[3];
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uint32_t attr;
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uint32_t tresh;
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@ -168,7 +168,7 @@ void omap_dss_reset(struct omap_dss_s *s)
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omap_dispc_interrupt_update(s);
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}
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static uint64_t omap_diss_read(void *opaque, target_phys_addr_t addr,
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static uint64_t omap_diss_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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struct omap_dss_s *s = (struct omap_dss_s *) opaque;
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@ -206,7 +206,7 @@ static uint64_t omap_diss_read(void *opaque, target_phys_addr_t addr,
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return 0;
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}
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static void omap_diss_write(void *opaque, target_phys_addr_t addr,
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static void omap_diss_write(void *opaque, hwaddr addr,
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uint64_t value, unsigned size)
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{
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struct omap_dss_s *s = (struct omap_dss_s *) opaque;
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@ -246,7 +246,7 @@ static const MemoryRegionOps omap_diss_ops = {
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static uint64_t omap_disc_read(void *opaque, target_phys_addr_t addr,
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static uint64_t omap_disc_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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struct omap_dss_s *s = (struct omap_dss_s *) opaque;
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@ -371,7 +371,7 @@ static uint64_t omap_disc_read(void *opaque, target_phys_addr_t addr,
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return 0;
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}
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static void omap_disc_write(void *opaque, target_phys_addr_t addr,
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static void omap_disc_write(void *opaque, hwaddr addr,
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uint64_t value, unsigned size)
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{
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struct omap_dss_s *s = (struct omap_dss_s *) opaque;
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@ -502,11 +502,11 @@ static void omap_disc_write(void *opaque, target_phys_addr_t addr,
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s->dispc.invalidate = 1;
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break;
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case 0x080: /* DISPC_GFX_BA0 */
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s->dispc.l[0].addr[0] = (target_phys_addr_t) value;
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s->dispc.l[0].addr[0] = (hwaddr) value;
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s->dispc.invalidate = 1;
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break;
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case 0x084: /* DISPC_GFX_BA1 */
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s->dispc.l[0].addr[1] = (target_phys_addr_t) value;
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s->dispc.l[0].addr[1] = (hwaddr) value;
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s->dispc.invalidate = 1;
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break;
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case 0x088: /* DISPC_GFX_POSITION */
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@ -543,7 +543,7 @@ static void omap_disc_write(void *opaque, target_phys_addr_t addr,
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s->dispc.l[0].wininc = value;
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break;
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case 0x0b8: /* DISPC_GFX_TABLE_BA */
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s->dispc.l[0].addr[2] = (target_phys_addr_t) value;
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s->dispc.l[0].addr[2] = (hwaddr) value;
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s->dispc.invalidate = 1;
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break;
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@ -602,11 +602,11 @@ static void omap_rfbi_transfer_stop(struct omap_dss_s *s)
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static void omap_rfbi_transfer_start(struct omap_dss_s *s)
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{
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void *data;
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target_phys_addr_t len;
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target_phys_addr_t data_addr;
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hwaddr len;
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hwaddr data_addr;
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int pitch;
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static void *bounce_buffer;
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static target_phys_addr_t bounce_len;
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static hwaddr bounce_len;
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if (!s->rfbi.enable || s->rfbi.busy)
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return;
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@ -663,7 +663,7 @@ static void omap_rfbi_transfer_start(struct omap_dss_s *s)
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omap_dispc_interrupt_update(s);
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}
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static uint64_t omap_rfbi_read(void *opaque, target_phys_addr_t addr,
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static uint64_t omap_rfbi_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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struct omap_dss_s *s = (struct omap_dss_s *) opaque;
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@ -730,7 +730,7 @@ static uint64_t omap_rfbi_read(void *opaque, target_phys_addr_t addr,
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return 0;
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}
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static void omap_rfbi_write(void *opaque, target_phys_addr_t addr,
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static void omap_rfbi_write(void *opaque, hwaddr addr,
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uint64_t value, unsigned size)
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{
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struct omap_dss_s *s = (struct omap_dss_s *) opaque;
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@ -864,7 +864,7 @@ static const MemoryRegionOps omap_rfbi_ops = {
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static uint64_t omap_venc_read(void *opaque, target_phys_addr_t addr,
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static uint64_t omap_venc_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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if (size != 4) {
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@ -924,7 +924,7 @@ static uint64_t omap_venc_read(void *opaque, target_phys_addr_t addr,
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return 0;
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}
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static void omap_venc_write(void *opaque, target_phys_addr_t addr,
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static void omap_venc_write(void *opaque, hwaddr addr,
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uint64_t value, unsigned size)
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{
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if (size != 4) {
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@ -986,7 +986,7 @@ static const MemoryRegionOps omap_venc_ops = {
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static uint64_t omap_im3_read(void *opaque, target_phys_addr_t addr,
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static uint64_t omap_im3_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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if (size != 4) {
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@ -1012,7 +1012,7 @@ static uint64_t omap_im3_read(void *opaque, target_phys_addr_t addr,
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return 0;
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}
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static void omap_im3_write(void *opaque, target_phys_addr_t addr,
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static void omap_im3_write(void *opaque, hwaddr addr,
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uint64_t value, unsigned size)
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{
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if (size != 4) {
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@ -1041,7 +1041,7 @@ static const MemoryRegionOps omap_im3_ops = {
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struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta,
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MemoryRegion *sysmem,
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target_phys_addr_t l3_base,
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hwaddr l3_base,
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qemu_irq irq, qemu_irq drq,
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omap_clk fck1, omap_clk fck2, omap_clk ck54m,
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omap_clk ick1, omap_clk ick2)
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