motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-01 14:53:54 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

Rename target_phys_addr_t to hwaddr

Browse source 
target_phys_addr_t is unwieldly, violates the C standard (_t suffixes are
reserved) and its purpose doesn't match the name (most target_phys_addr_t
addresses are not target specific).  Replace it with a finger-friendly,
standards conformant hwaddr.

Outstanding patchsets can be fixed up with the command

  git rebase -i --exec 'find -name "*.[ch]"
                        | xargs s/target_phys_addr_t/hwaddr/g' origin

Signed-off-by: Avi Kivity <avi@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Avi Kivity 2012-10-23 12:30:10 +02:00 • committed by Anthony Liguori
parent 50d2b4d93f
commit a8170e5e97
383 changed files with 2240 additions and 2240 deletions
Download patch file Download diff file Expand all files Collapse all files

24
hw/omap_dma.c
View file

@ -31,7 +31,7 @@ struct omap_dma_channel_s {
int endian_lock[2];
int translate[2];
enum omap_dma_port port[2];
target_phys_addr_t addr[2];
hwaddr addr[2];
omap_dma_addressing_t mode[2];
uint32_t elements;
uint16_t frames;
@ -78,7 +78,7 @@ struct omap_dma_channel_s {
struct omap_dma_channel_s *sibling;
struct omap_dma_reg_set_s {
target_phys_addr_t src, dest;
hwaddr src, dest;
int frame;
int element;
int pck_element;
@ -914,7 +914,7 @@ static int omap_dma_ch_reg_write(struct omap_dma_s *s,
break;
case 0x06: /* SYS_DMA_CSR_CH0 */
OMAP_RO_REG((target_phys_addr_t) reg);
OMAP_RO_REG((hwaddr) reg);
break;
case 0x08: /* SYS_DMA_CSSA_L_CH0 */
@ -954,7 +954,7 @@ static int omap_dma_ch_reg_write(struct omap_dma_s *s,
break;
case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */
OMAP_RO_REG((target_phys_addr_t) reg);
OMAP_RO_REG((hwaddr) reg);
break;
case 0x1c: /* DMA_CDEI */
@ -1446,7 +1446,7 @@ static int omap_dma_sys_read(struct omap_dma_s *s, int offset,
return 0;
}
static uint64_t omap_dma_read(void *opaque, target_phys_addr_t addr,
static uint64_t omap_dma_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_dma_s *s = (struct omap_dma_s *) opaque;
@ -1494,7 +1494,7 @@ static uint64_t omap_dma_read(void *opaque, target_phys_addr_t addr,
return 0;
}
static void omap_dma_write(void *opaque, target_phys_addr_t addr,
static void omap_dma_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_dma_s *s = (struct omap_dma_s *) opaque;
@ -1618,7 +1618,7 @@ static void omap_dma_setcaps(struct omap_dma_s *s)
}
}
struct soc_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs,
struct soc_dma_s *omap_dma_init(hwaddr base, qemu_irq *irqs,
MemoryRegion *sysmem,
qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,
enum omap_dma_model model)
@ -1692,7 +1692,7 @@ static void omap_dma_interrupts_4_update(struct omap_dma_s *s)
qemu_irq_raise(s->irq[3]);
}
static uint64_t omap_dma4_read(void *opaque, target_phys_addr_t addr,
static uint64_t omap_dma4_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_dma_s *s = (struct omap_dma_s *) opaque;
@ -1842,7 +1842,7 @@ static uint64_t omap_dma4_read(void *opaque, target_phys_addr_t addr,
}
}
static void omap_dma4_write(void *opaque, target_phys_addr_t addr,
static void omap_dma4_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_dma_s *s = (struct omap_dma_s *) opaque;
@ -1988,12 +1988,12 @@ static void omap_dma4_write(void *opaque, target_phys_addr_t addr,
break;
case 0x1c: /* DMA4_CSSA */
ch->addr[0] = (target_phys_addr_t) (uint32_t) value;
ch->addr[0] = (hwaddr) (uint32_t) value;
ch->set_update = 1;
break;
case 0x20: /* DMA4_CDSA */
ch->addr[1] = (target_phys_addr_t) (uint32_t) value;
ch->addr[1] = (hwaddr) (uint32_t) value;
ch->set_update = 1;
break;
@ -2040,7 +2040,7 @@ static const MemoryRegionOps omap_dma4_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
struct soc_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs,
struct soc_dma_s *omap_dma4_init(hwaddr base, qemu_irq *irqs,
MemoryRegion *sysmem,
struct omap_mpu_state_s *mpu, int fifo,
int chans, omap_clk iclk, omap_clk fclk)