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Rename target_phys_addr_t to hwaddr

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target_phys_addr_t is unwieldly, violates the C standard (_t suffixes are
reserved) and its purpose doesn't match the name (most target_phys_addr_t
addresses are not target specific).  Replace it with a finger-friendly,
standards conformant hwaddr.

Outstanding patchsets can be fixed up with the command

  git rebase -i --exec 'find -name "*.[ch]"
                        | xargs s/target_phys_addr_t/hwaddr/g' origin

Signed-off-by: Avi Kivity <avi@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Avi Kivity 2012-10-23 12:30:10 +02:00 • committed by Anthony Liguori
parent 50d2b4d93f
commit a8170e5e97
383 changed files with 2240 additions and 2240 deletions
Download patch file Download diff file Expand all files Collapse all files

24
hw/apb_pci.c
View file

@ -87,7 +87,7 @@ typedef struct APBState {
static void pci_apb_set_irq(void *opaque, int irq_num, int level);
static void apb_config_writel (void *opaque, target_phys_addr_t addr,
static void apb_config_writel (void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
APBState *s = opaque;
@ -152,7 +152,7 @@ static void apb_config_writel (void *opaque, target_phys_addr_t addr,
}
static uint64_t apb_config_readl (void *opaque,
target_phys_addr_t addr, unsigned size)
hwaddr addr, unsigned size)
{
APBState *s = opaque;
uint32_t val;
@ -212,7 +212,7 @@ static const MemoryRegionOps apb_config_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
static void apb_pci_config_write(void *opaque, target_phys_addr_t addr,
static void apb_pci_config_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
APBState *s = opaque;
@ -222,7 +222,7 @@ static void apb_pci_config_write(void *opaque, target_phys_addr_t addr,
pci_data_write(s->bus, addr, val, size);
}
static uint64_t apb_pci_config_read(void *opaque, target_phys_addr_t addr,
static uint64_t apb_pci_config_read(void *opaque, hwaddr addr,
unsigned size)
{
uint32_t ret;
@ -234,25 +234,25 @@ static uint64_t apb_pci_config_read(void *opaque, target_phys_addr_t addr,
return ret;
}
static void pci_apb_iowriteb (void *opaque, target_phys_addr_t addr,
static void pci_apb_iowriteb (void *opaque, hwaddr addr,
uint32_t val)
{
cpu_outb(addr & IOPORTS_MASK, val);
}
static void pci_apb_iowritew (void *opaque, target_phys_addr_t addr,
static void pci_apb_iowritew (void *opaque, hwaddr addr,
uint32_t val)
{
cpu_outw(addr & IOPORTS_MASK, bswap16(val));
}
static void pci_apb_iowritel (void *opaque, target_phys_addr_t addr,
static void pci_apb_iowritel (void *opaque, hwaddr addr,
uint32_t val)
{
cpu_outl(addr & IOPORTS_MASK, bswap32(val));
}
static uint32_t pci_apb_ioreadb (void *opaque, target_phys_addr_t addr)
static uint32_t pci_apb_ioreadb (void *opaque, hwaddr addr)
{
uint32_t val;
@ -260,7 +260,7 @@ static uint32_t pci_apb_ioreadb (void *opaque, target_phys_addr_t addr)
return val;
}
static uint32_t pci_apb_ioreadw (void *opaque, target_phys_addr_t addr)
static uint32_t pci_apb_ioreadw (void *opaque, hwaddr addr)
{
uint32_t val;
@ -268,7 +268,7 @@ static uint32_t pci_apb_ioreadw (void *opaque, target_phys_addr_t addr)
return val;
}
static uint32_t pci_apb_ioreadl (void *opaque, target_phys_addr_t addr)
static uint32_t pci_apb_ioreadl (void *opaque, hwaddr addr)
{
uint32_t val;
@ -351,8 +351,8 @@ static int apb_pci_bridge_initfn(PCIDevice *dev)
return 0;
}
PCIBus *pci_apb_init(target_phys_addr_t special_base,
target_phys_addr_t mem_base,
PCIBus *pci_apb_init(hwaddr special_base,
hwaddr mem_base,
qemu_irq *ivec_irqs, PCIBus **bus2, PCIBus **bus3,
qemu_irq **pbm_irqs)
{